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GENERAL ADJUSTMENTS
SPECIFIC INFORMATIONS
4. TELETEXT (P2) CIRCUIT
4-1 OUTLINE
TELETEXT circuit extracts several data of input video signal, and decode them to generate display signal. It works as Stand-
alone Subsystem. Major feature of TELETEXT circuit is as follows.
- Digital Data Slicer of VBI (Vertical Blanking Interval) data
- Display 50/60/100/120Hz mode
- Display Progressive mode (Only SAA5695HL)
- Decode & Display Teletext (Level 1.5)
- Supporting character set of Pan-Euro/ Cyrillic/ Arabic/ Farci
- Supporting Asia language as shown in Table 4-1-1 and Table 4-1-2
Table 4-1-1 Supported Teletext Language for Austraria (A) and Singapore (E)
Text Character
No Selection
West Europe
Text Language
English/German/Dutch/Flemish/Hungarian/Swedish/Finnish/
Danish/Norwegian/Italian/French/Spanish/Portuguese/Turkish
Text Language
Polish/German/Dutch/Flemish/Hungarian/Lituanian/Russian/
Bulgarian/Serbian/Croatian/Slovenian/Czech/Slovak/Estonian
Polish/German/Dutch/Flemish/Estonian/Lituanian/Lettish/French/
Ukrainian
English/German/Dutch/Flemish/Hungarian/Swedish/Finnish/
Danish/Norwegian/Italian/French/Spanish/Portuguese/Turkish
English/French/Turkish/Arabic
English/French/Turkish/Iranian/Persian
Table 4-1-2 Supported Teletext Language for Russian (R)/Middle East (M)
Text Character
Character 1
Russian
Character 2
Ukrainian
Character 3
West Europe
Character 4
Arabic
Character 5
Farsi
4-2 CIRCUIT OPERATION
The Teletext subsystem receives quite simple commands from mains system (QA01) via serial I
2
C bus, and takes control
over the Teletext Pages display.
Block diagram of Teletext circuit is shown in Fig.4-2-1. Video signal that is input to pin 7 of UNIT from H001 is changed to
1.0V(p-p) signal that is improved by the ATT & Negative Group Delay Compensation Filter, and it is supplied to pin 31
and 32 of QT01.
The display signal is output at pins 11, 14 and 15 in the Analogue 0.6V DC 0.4 to 0.56V(p-p) defined in subdata
TXTG (0.4V(p-p) at 50Hz Scanning, 0.56V(p-p) at 100Hz Scanning), and at pin 10 in the Digital 3.3V(p-p) of positive
polarity. the display signal timing is synchronized by Horizontal and Vertical signal from pins 4 and 5 of UNIT. The timing
and polarity of Horizontal and Vertical is defined in subdata TXTS.
The RGB output is sent to V/C/D IC and the screen is displayed.
Summary of Contents for 57VW9UA
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Page 67: ... 69 70 SIGNAL BOARD PD0958 BOTTOM FOIL SIDE ...
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Page 71: ... 77 SVM B BOARD PD1053 6 BOTTOM FOIL SIDE WOW BOARD PD0961 BOTTOM FOIL SIDE ...
Page 73: ... 79 BEP BOARD PD01057 2 BOTTOM FOIL SIDE TEXT P2 BOARD PD0963 BOTTOM FOIL SIDE ...
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Page 88: ... SHEET 3 9 57VW9UE SIGNAL SOUND 57VW9UA 12 0 9 0 19 0 7 0 7 1 0 0 19 1 0 19 36 0 0 0 0 ...
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Page 93: ... SHEET 4 9 SIGNAL IF 57VW9UE 57VW9UA 4 2 4 2 0 4 3 4 3 4 3 4 3 32 0 32 0 5 0 5 0 0 9 0 0 0 ...
Page 96: ... SHEET 5 9 57VW9UE SIGNAL M CON 57VW9UA 5Vp p 5Vp p fV 5Vp p 5Vp p 5Vp p 5Vp p SD SDA SCL SCL ...
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Page 100: ... SHEET 7 9 SIGNAL D CONV 57VW9UE 57VW9UA 0 5 0 5 0 5 0 0 4 5 4 5 4 5 4 5 0 ...
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Page 109: ...DEF CONV 1 3 57VW9UE SHEET 1 3 57VW9UA ...
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