Toshiba 27WLT56B Service Manual Download

Page: 69 / 84

27” TFT TV Service Manual

05/09/2005

BLOCK DIAGRAM - IDTV PART

CONTROLLER

MPEG DECODER

STi5518

DIGITAL

TUNER

DIGITAL

FRONTEND

ST0360

+12V

+5V

3.3V

2.5V

1.8V

S+5V

S3.3V

S2.5V

S1.8V

FC_DATA(0-7)
FC_CLK
FC_SYNC
FC_VALID

CMD(0-7)
CMD_CLK
CMD_SYNC
CMD_VALID

BT-601 8-bit, HS,VS

PCM/I2S

AUDIO

L/R

CI CONNECTOR

EMI DRAM

SMI DRAM

ASH

PROM

ADR&DATA

LAT

ADR

(0-14)
CPU_
DATA

(0-7)

MDIA_D(0-

MDOA_D(0-

MA_A(0-1

CARD

INTERFACE

STV0700

PCM
DAC

CVBS

TO VIDEO

MATRIX

AUDIO

SWITCH

TO GM6015 PORT B

FROM

POWER

SUPPLY

Serial Interface RX,TX,IRQ

TO SDA 5550 CONTROLLER

Summary of Contents for 27WLT56B

Page 1: ...TOSHIBA 27WLT56B SERVICE MANUAL ...

Page 2: ... TLC7733 11 12 8 74LVC257A 12 12 9 74LVC14A 12 12 10 LM1117 13 12 11 IRF7314 IRF7316 14 12 12 MC34063A 15 12 13 LM2576 52kHz Simple 3A Buck Regulator 16 12 14 DS90C385 17 12 15 MSP34X1G 19 12 16 TPA3002D 22 12 17 TDA1308 22 12 18 PI5V330 23 12 19 MST9883 23 12 20 SAA7118E 25 12 21 TPS72501 30 12 22 TSOP1136 32 12 23 PCF8591 32 12 24 PW1231 33 12 25 PW181 34 12 26 SIL1169 35 12 27 SDRAM 4M x 16 MT4...

Page 3: ... TFT TV Service Manual 05 09 2005 14 SERVICE MENU SETTINGS 58 14 1 display menu 58 14 2 calibration menu 60 14 3 deinterlacer menu 62 14 4 factory settings menu 64 15 BLOCK DIAGRAMS 65 16 CIRCUIT DIAGRAMS 67 ...

Page 4: ...ral description of UV1316 The UV1316 tuner belongs to the UV 1300 family of tuners which are designed to meet a wide range of applications It is a combined VHF UHF tuner suitable for CCIR systems B G H L L I and I The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient Features of UV1316 1 Member of the UV1300 ...

Page 5: ...dard EIA J and the FM Stereo Radio standard Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA J The MSP34x1G has optimum stereo performance without any adjustments 5 VIDEO SWITCH TEA6415 In case of three or more external sources are used the video switch IC TEA6415 is used The main function of this device is to switch 8 video input source...

Page 6: ...iplexed to control up to five 2 wire serial ports The slave 2 wire interface is designed for HDCP use only and requires the use of HDCP Image Processors On chip RAM of up to 64 Kbytes is available A complete microprocessor system can be implemented simply by adding external ROM The on chip processor can be disabled to allow external processor control of all internal functions 9 SERIAL ACCESS CMOS ...

Page 7: ...lloy Pin configuration 1 Input 2 Input ground 3 Chip carrier ground 4 Output 5 Output 12 IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM TDA9886 TEA6415C 24C32 SAA5264 LM317T ST24LC21 TLC7733 74LVC257A 74LVC14A LM1117 IRF7314 IRF7316 MC34063A LM2576 DS90C385 MSP3411G TPA3002D TDA1308 PI5V330 MST9883 SAA7118E TPS72501 TSOP1136 PCF8591 PW1231 PW181 SIL1169 SDRAM 4M x 16 MT48LC4M16A2TG 75 FLASH ASM3P2814 ...

Page 8: ...FC bits via I2 C bus readable TakeOver Point TOP adjustable via I2 C bus or alternatively with potentiometer Fully integrated sound carrier trap for 4 5 5 5 6 0 and 6 5 MHz controlled by FM PLL oscillator Sound IF SIF input for single reference Quasi Split Sound QSS mode PLL controlled SIF AGC for gain controlled SIF amplifier single reference QSS mixer able to operate in high performance single r...

Page 9: ...s of 16 bits are necessary to determine one configuration In other case 1 word of 16 bits is necessary to determine one configuration 12 2 2 Features 20MHz Bandwidth Cascadable with another TEA6415C Internal address can be changed by pin 7 voltage 8 Inputs CVBS RGB MAC CHROMA 6 Outputs Possibility of MAC or chroma signal for each input by switching off the clamp with an external resistor bridge Bu...

Page 10: ...mmercial C 0 C to 70 C Industrial I 40 C to 85 C Automotive E 40 C to 125 C 12 3 2 Description The Microchip Technology Inc 24C32A is a 4K x 8 32K bit Serial Electrically Erasable PROM It has been developed for advanced low power applications such as personal communications or data acquisition The 24C32A also has a page write capability of up to 32 bytes of data The 24C32A is capable of both rando...

Page 11: ...rd colour decoder ICs current source Versatile 8 bit open drain Input Output I O expander 5 V tolerant Single 12 MHz crystal oscillator 3 3 V supply voltage SAA5264 features Automatic detection of transmitted pages to be selected by page up and page down 8 Page fastext decoder Table Of Pages TOP decoder with Basic Top Table BTT and Additional Information Tables AITs 4 Page user defined list mode 1...

Page 12: ...en drain active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display 30 I O P3 4 PWM7 described above VDDA 31 analog supply voltage 3 3 V B 32 O Blue colour information pixel rate output G 33 O Green colour information pixel rate output R 34 O Red colour information pixel rate output VDS 35 O video data switch push pull output for pixel rate fast b...

Page 13: ... Control 12 6 ST24LC21 12 6 1 Description The ST24LC21 is a 1K bit electrically erasable programmable memory EEPROM organized by 8 bits This device can operate in two modes Transmit Only mode and I2 C bidirectional mode When powered the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK The device will switch to the I2 C bidirectional mo...

Page 14: ...LC77xx has a fixed SENSE threshold voltage set by an internal voltage divider When SENSE voltage drops below the threshold voltage the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time td has expired In addition to the power on reset and undervoltage supervisor function the TLC77xx adds power down control support for static RAM When...

Page 15: ...mentation of a 4 pole 2 position switch where the position of the switch is determined by the logic levels applied to S The outputs are forced to a high impedance OFF state when OE is HIGH 12 8 3 Pin Description PIN NUMBER SYMBOL DESCRIPTION 1 S Common data select input 2 5 11 14 1 0 to 4 0 Data inputs from source 0 3 6 10 13 1 1 to 4 1 Data outputs from source 1 4 7 9 12 1Y to 4Y 3 State multiple...

Page 16: ...d 5V The LM1117 offers current limiting and thermal shutdown Its circuit includes a zener trimmed bandgap reference to as sure output voltage accuracy to within 1 The LM1117 series is available in SOT 223 TO 220 and TO 252 D PAK packages A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability 12 10 2 Features Available in 1 8V 2 5V 2 85V 3 3V ...

Page 17: ...314 IRF7316 Absolute Maximum Ratings TA 25 C Unless Otherwise Noted IRF7314 Symbol Maximum Units Drain Source Voltage VDS 20 Gate Source Voltage VGS 12 V TA 25 C 5 3 Continuous Drain Current TA 70 C I 4 3 Pulsed Drain Current IDM 21 Continuous Source Current Diode Conduction IS 2 5 A TA 25 C 2 0 Maximum Power Dissipation P 1 3 W Single Pulse Avalanche Energy EAS 150 mJ Avalanche Current IAR 2 9 A ...

Page 18: ...rolled duty cycle oscillator with an active current limit circuit driver and high current output switch This series was specifically designed to be incorporated in Step Down and Step Up and Voltage Inverting applications with a minimum number of external components Refer to Application Notes AN920A D and AN954 D for additional design information Features Operation from 3 0 V to 40 V Input Low Stan...

Page 19: ...lly reduces the size of the heat sink and in many cases no heat sink is required A standard series of inductors available from several different manufacturers are ideal for use with the LM2576 series This feature greatly simplifies the design of switch mode power supplies The feedback voltage is guaranteed to 2 tolerance for adjustable versions and the output voltage is guaranteed to 3 for fixed v...

Page 20: ... FPFRAME DRDY are transmitted at a rate of 595 Mbps per LVDS data channel Using an 85 MHz clock the data throughput is 297 5 Mbytes sec Also available is the DS90C365 that converts 21 bits of LVCMOS LVTTL data into three LVDS Low Voltage Differential Signaling data streams Both transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin A Rising edge or Fal...

Page 21: ...OWN I 1 TTL level input Assertion low input TRI STATES the outputs ensuring low current at power down Vcc I 3 Power supply pins for TTL inputs GND I 4 Ground pins for TTL inputs PLL Vcc I 1 Power supply pin for PLL PLL GND I 2 Ground pins for PLL LVDS Vcc I 1 Power supply pin for LVDS outputs LVDS GND I 3 Ground pins for LVDS outputs Pin Name I O No Description TxIN I 28 TTL level input TxOUT O 4 ...

Page 22: ...o the standard recommended by the Broadcast Television Systems Committee BTSC The DBX noise reduction or alternatively Micronas Noise Reduction MNR is performed alignment free Other processed standards are the Japanese FM FM multiplex standard EIA J and the FM Stereo Radio standard Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA J The M...

Page 23: ...not used leave vacant OBL obligatory connect as described in circuit diagram DVSS if not used connect to DVSS AHVSS connect to AHVSS Pin No Pin Name Type Connection if not used Short Description PLCC 68 pin PSDIP 64 pin PSDIP 52 pin PQFP 80 pin PLQFP 64 pin 1 16 14 9 8 ADR_WS OUT LV ADR word strobe 2 NC LV Not connected 3 15 13 8 7 ADR_DA OUT LV ADR Data Output 4 14 12 7 6 I2S_DA_IN1 IN LV I 2 S1 ...

Page 24: ...nected 44 40 34 40 32 CAPL_M OBL Volume capacitor MAIN 45 39 33 39 31 AHVSUP OBL Analog power supply 8V 46 38 32 38 30 CAPL_A OBL Volume capacitor AUX 47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1 left 48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1 right 49 35 29 35 27 VREF1 OBL Reference ground 1 50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2 left 51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2 r...

Page 25: ...ted 5 V Supply Output for Powering TPA6110A2 Space Saving Thermally Enhanced PowerPAD Packaging Thermal and Short Circuit Protection 12 16 2 Pin Connection 12 17 TDA1308 12 17 1 General Description The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable ...

Page 26: ...itler can be implemented by superimposing the output of a character generator on a standard composite video background 12 19 MST9883 12 19 1 General Description The MST9883C is a fully integrated analog interface for digitizing high resolution RGB graphics signals from PC s and workstations With a sampling rate capability of up to 140 MHz it can accurately support display resolutions up to 1280x10...

Page 27: ...24 27 TFT TV Service Manual 05 09 2005 12 19 3 Pin Descriptions ...

Page 28: ...emory or just to provide digital baseband video to any picture improvement processing 12 20 2 Features Video acquisition clock Up to sixteen analog CVBS split as desired all of the CVBS inputs optionally can be used to convert e g Vestigial Side Band VSB signals Up to eight analog Y C inputs split as desired Up to four analog component inputs with embedded or separate sync split as desired Four on...

Page 29: ...aces Real time signal port R port inclusive continuous line locked reference clock and real time status information supporting RTC level 3 1 refer to document RTC Functional Specification for details Bidirectional expansion port X port with half duplex functionality D1 8 bit Y CB CR Output from decoder part real time and unscaled Input to scaler part e g video from MPEG decoder extension to 16 bit...

Page 30: ...not connect reserved for future extensions and for testing TEST8 C4 NC do not connect reserved for future extensions and for testing VDDD1 C5 P digital supply voltage 1 peripheral cells TRST C6 I pu test reset input active LOW for boundary scan test with internal pull up notes 2 3 and 4 XRH C7 I O horizontal reference I O expansion port VDDD2 C8 P digital supply voltage 2 core VDDD3 C9 P digital s...

Page 31: ...IPD0 G14 O LSB of image port data output AI2D H1 I differential input for ADC channel 2 pins AI24 to AI21 AI23 H2 I analog input 23 VSSA2 H3 P ground for analog inputs AI2x VDDA2 H4 P analog supply voltage for analog inputs AI2x IPD2 H11 O MSB 5 of image port data output VDDD7 H12 P digital supply voltage 7 peripheral cells IPD4 H13 O MSB 3 of image port data output IPD3 H14 O MSB 4 of image port ...

Page 32: ...aster external clock input FSW M13 I pd fast switch blanking with internal pull down inserts component inputs into CVBS signal ICLK M14 I O clock output signal for image port or optional asynchronous back end clock input TEST13 N1 NC do not connect reserved for future extensions and for testing TEST14 N2 I pu do not connect reserved for future extensions and for testing TEST15 N3 I pd do not conne...

Page 33: ... 21 1 General Description The TPS725xx family of 1 A low dropout LDO linear regulators has fixed voltage options available that are commonly used to power the latest DSPs FPGAs and microcontrollers An adjustable option ranging from 1 22 V to 5 5 V is also available The integrated supervisory circuitry provides an active low RESET signal when the output falls out of regulation The no capacitor any ...

Page 34: ... 1 2 V to 5 5 V Input Voltage Down to 1 8 V Low 170 mV Dropout Voltage at 1 A TPS72525 Stable With Any Type Value Output Capacitor Integrated Supervisor SVS With 50 ms RESET Delay Time Low 210 µA Ground Current at Full Load TPS72525 Less than 1 µA Standby Current 2 Output Voltage Tolerance Over Line Load and Temperature 40C to 125C Integrated UVLO Thermal and Overcurrent Protection 5 Lead SOT223 5...

Page 35: ...om the device are transferred serially via the two line bidirectional I2 C bus The functions of the device include analog input multiplexing on chip track and hold function 8 bit analog to digital conversion and an 8 bit digital to analog conversion The maximum conversion rate is given by the maximum speed of the I2 C bus 12 23 2 Features Single power supply Operating supply voltage 2 5 V to 6 V L...

Page 36: ...elworks patented deinterlacing scaling and video enhancement algorithms The PW1231 accepts industry standard video formats and resolutions and converts the input into any desired output format The video algorithms are highly efficient providing excellent quality video The PW1231 Video SignalProcessor combines many functions into a single device including memory controller auto configuration and ot...

Page 37: ...n chip A separate memory is dedicated to storage of on screen display images and CPU general purpose use Advanced video processing techniques are supported using the internal frame buffer including motion adaptive temporal deinterlacing with film mode detection When used in combination with the new third generation scaler this advanced video processing technology delivers the highest quality video...

Page 38: ...implify manufacturing and provide the highest level of security 12 26 2 Features Integrated 25 165MHz PanelLink DVI 1 0 compliant core supports VGA to UXGA resolutions Supports HDTV resolutions 720p 1080i 1080p Integrated HDCP decryption engine for viewing protected content Pre programmed HDCP keys provide highest level of key security simplify manufacturing Backwards compatible with SiI 161B SiI ...

Page 39: ...D or WRITE command are used to select the starting column location for the burst access The SDRAM provides for programmable READ or WRITE burst lengths of 1 2 4 or 8 locations or the full page with a burst terminate option An auto precharge function may be enabled to provide a self timed row precharge that is initiated at the end of the burst sequence The 64Mb SDRAM uses an internal pipelined arch...

Page 40: ...k selection on systems with multiple banks CS is considered part of the command code 16 17 18 WE CAS RAS Input Command Inputs WE CAS and RAS along with CS define the command being entered 39 x4 x8 DQM 15 39 x16 DQML DQMH Input Input Output Mask DQM is an input mask signal for write accesses and an output enable signal for read accesses Input data is masked when DQM is sampled HIGH during a WRITE c...

Page 41: ...t required to control the memory is consistent with JEDEC standards The blocks in the memory are asymmetrically arranged ee Figures 5 and 6 Block Addresses he first or last 64 KBytes have been divided into our additional blocks The 16 KByte Boot Block can be used for small initialization code to start the microprocessor the two 8 KByte Parameter Blocks can be used for parameter storage and the rem...

Page 42: ...litudes of its harmonics This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators Lowering EMI by increasing a signal s bandwidth is called spread spectrum clock generation The ASM3P28XX uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all digital m...

Page 43: ...CC OPR 1 65V to 5 5V 1 2V Data Retention IMPROVED LATCH UP IMMUNITY 12 30 2 Description The 74LX1G86 is a low voltage CMOS SINGLE EXCLUSIVE OR GATE fabricated with sub micron silicon gate and double layer metal wiring C2 MOS technology Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage This device can be used to interface 5V t...

Page 44: ...annel analogue multiplexer demultiplexer with a common enable input VCC and GND are the supply voltage pins for the digital control inputs The VCC to GND ranges are 4 5 to 5 5 V for HCT The analog inputs outputs nY0 and nY1 and nZ can swing between VCC as a positive limit and VEE as a negative limit VCC VEE may not exceed 10 0 V 12 31 2 Pin Description ...

Page 45: ...18 is ideal for set top boxes featuring trick modes such as live TV recording pausing and time shifting The STi5518 is backward compatible with the popular STi5500 set top box decoder allowing easy migration from the previous generation The high level of integration in a single PQFP 208 package makes the STi5518 ideally suited for low cost high volume set top box applications 13 2 MAX232_SMD 13 2 ...

Page 46: ...cated in silicon gate C2 MOS technology It has the same high speed performance of LSTTL combined with true CMOS low power consumption As the internal circuit is composed of a single stage inverter it can be used in crystal oscillator All inputs are equipped with circuits against static discharge and transient excess voltage 13 3 2 Pin Description ...

Page 47: ...er only in the supported interface format The CS4334 family is based on delta sigma modulation where the modulator output controls the reference voltage input to an ultra linear analogue low pass filter This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency The CS4334 family contains on chip digital de emphasis operat...

Page 48: ... clock cycle Range of operating frequencies programmable latencies allows the same device to be useful for a variety of high bandwidth high performance memory system applications 13 6 2 Features JEDEC standard 3 3V power supply LVTTL compatible with multiplexed address Four banks Pulse RAS MRS cycle with address key programs All inputs are sampled at the positive going edge of the system clock Clo...

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Page 50: ...OM compatibility MXIC Flash technology reliably stores memory contents even after 100 000 erase and program cycles The MXIC cell is designed to optimize the erase and programming mechanisms In addition the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling The MX29LV160T B MX29LV160AT AB uses a 2 7V 3 6V VCC s...

Page 51: ...ware Data Protection 32 Byte Page Write Mode Partial Page Writes Allowed Self Timed Write Cycle 10 ms max High Reliability Automotive Grade and Extended Temperature Devices Available 8 Pin JEDEC PDIP 8 Pin JEDEC SOIC 8 Pin EIAJ SOIC and 8 pin TSSOP Packages 13 8 3 Pin Description SERIAL CLOCK SCL The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data...

Page 52: ...ation eliminates the need for external components when using wide band AGC tuners In addition to all the demodulation and FEC forward error correction functions required for recovery of the QAM modulated bit streams with very low BER it also includes several features that give easy and immediate access to various quality monitoring parameters or lock status The STV0360 also provides output such as...

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Page 55: ...RESET output requires a pull up resistor that can be connected to a voltage higher than VCC The MAX803 MAX809 have an active low RESET output while the MAX810 has an active high RESET output The reset comparator is designed to ignore fast transients on VCC and the outputs are guaranteed to be in the correct logic state for VCC down to 1V Low supply current makes the MAX803 MAX809 MAX810 ideal for ...

Page 56: ...and Set Top Box manufacturers that want to quickly implement the Common Interface The STV0700 includes the necessary I Os to interface to the MPEG Transport stream generated by the receiver demodulator and daisy chain it through two independent Common Interface modules and back to the demultiplexer The STV0700 interfaces with major digital TV receiver microprocessors An I2 C bus is used for initia...

Page 57: ...rtion Automatic and Reset VCC handling 3 3V 5V tolerant I O buffers IEEE 1149 1 Boundary Scan Compliant Test Access Port Host microprocessor Interface Universal Control Signal Generator UCSG o PC Card control signals generation o Supports PowerPC ARM ST20 68xxx TMS LSI 64008 TC81220F IDTR3041 host microprocessors I2 C port o STV0700 Set up o Slot selection o Cascade mode management up to 4STV0700 ...

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Page 61: ... the service menu press MENU button Entire service menu parameters of Plasma TV are listed below 14 1 display menu By pressing buttons select the first icon display menu appears on the screen blank color By pressing c d button select blank color Press e f button to set the blank color The options are black red green and blue panel Displays panel resolution power on time Displays total working time...

Page 62: ...ess e f button to set the subwoofer level Subwoofer level can be adjusted between 0 and 32 agc adjustment Adjustment for automatic gain control of tuner By pressing c d button select agc adjustment Press e f button to set the agc adjustment Agc adjustment can be adjusted between 0 and 31 carrier mute By pressing c d button select carrier mute Press e f button to enable or disable the sound carrier...

Page 63: ...If color temp is set as user then R G B settings can be adjusted By pressing c d button select Red Green or Blue Press f button to increase the color value Press e button to decrease the color value R G B values can be adjusted between 0 and 63 video format By pressing c d button select video format Press e f button to set the video format The options are auto ntsc pal secam and ntsc japan color t...

Page 64: ...ressing c d button select solid field level Press f button to increase or e button to decrease the solid field level Solid field level can be adjusted between 0 and 64 factory reset By pressing c d button select factory reset Press OK button to return to the factory setting values main tuner By pressing c d button select main tuner Press e f button to set a tuner as main tuner pip tuner By pressin...

Page 65: ...By pressing c d button select dlti DLTI can be adjusted between 0 and 255 by pressing e f button luminance peaking By pressing c d button select luminance peaking Luminance peaking can be set to on or off by pressing e f button film mode By pressing c d button select film mode Film mode speed can be set to on or off by pressing e f button black expansion dcti dlti luminance peaking film mode film ...

Page 66: ...ld By pressing c d button select nr threshold Nr threshold can be set to low or high by pressing e f button noise reduction By pressing c d button select noise reduction Noise reduction can be adjusted between 0 and 255 by pressing e f button lai level By pressing c d button select lai level Lai level can be set to 0 1 or 2 by pressing e f button sharpness By pressing c d button select sharpness S...

Page 67: ...en Brightness contrast sharpness color volume and headphone volume factory settings can be seen in this menu When factory reset is selected in the calibration menu the values in the factory settings menu will be seen in the TV menus contrast sharpness hp volume factory settings 50 down to change factory settings 6 33 brightness 77 color 31 volume 21 ...

Page 68: ...3W Flash Memory A0 A19 20 D0 D15 16 RGB 24 DS90C385 LVDS TX S Video_Y_IN S Video_C_IN TEA6415 Video Switch SC1_V_OUT SC1_V_IN SC2_V_IN SC2_V_OUT SC1_PIN8 SC2_PIN8 SAA5264 TXT Decoder 24C32 E2PROM SCL SDA TXT_CVBS TXT R G B FB 4 TXT R G B FB 4 2 1 DVI_RX 0 C Vx to Main Vx to Main Vx to Pip Vx to Pip Main_CVBS Main_CVBS Pip_CVBS Pip_CVBS TXT_CVBS YUV 16 YUV 16 GRGB VRGB RGB 24 RGB 48 GCOAST PW181A D...

Page 69: ... 7 FC_CLK FC_SYNC FC_VALID CMD 0 7 CMD_CLK CMD_SYNC CMD_VALID BT 601 8 bit HS VS PCM I2S AUDIO L R CI CONNECTOR EMI DRAM SMI DRAM FLASH I2C I2C EE PROM ADR DATA LATCH ADR 0 14 CPU_ DATA 0 7 MDIA_D 0 7 MDOA_D 0 7 MA_A 0 14 CI CARD INTERFACE STV0700 I2 C I2C PCM DAC I2 C CVBS TO VIDEO MATRIX TO AUDIO SWITCH TO GM6015 PORT B FROM POWER SUPPLY Serial Interface RX TX IRQ TO SDA 5550 CONTROLLER ...

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