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2 gm5221 Pinout
The gm5221 devices are packaged in a 208-pin Plastic Quad Flat Pack (PQFP).
N/
C
N/
C
DC
LK
JT
AG
_
R
ES
E
T
RES
ERVED
RES
ERVED
RES
ERVED
RES
ERVED
RES
ERVED
RES
ERVED
RES
ERVED
JT
AG
_
T
DO
RES
ERVED
JT
AG
_
T
DI
PP
W
R
PBIAS
GP
IO1
5
RES
ERVED
HO
ST
_SCL
/UART
_
DI
HO
ST
_SDA/U
A
RT
_
DO
RV
D
D_
3
.3
CR
V
S
S
CV
D
D_
1
.8
CR
V
S
S
DDC_
SCL_
V
G
A
DDC_
S
D
A
_
V
G
A
DD
C_SCL
_DVI
DDC
_SDA_DVI
GP
IO
0
GP
IO
1
GP
IO
2
GP
IO
3
GP
IO
4
CV
D
D_
1
.8
CR
V
S
S
GP
IO
5
GP
IO
6
GPI
O
7
/IRQ
in
GP
IO
8/
IR
Qo
ut
GP
IO
9/
S
C
L
GPI
O
10/
SDA
CR
V
S
S
RV
D
D_
3
.3
CV
D
D_
1
.8
CR
V
S
S
GPI
O
11
/PWM
0
GPI
O
12
/PWM
1
GPI
O
13
/PWM
2
GPI
O
14
/PWM
3
G
P
IO
16
/V
D
A
TA
7
G
P
IO
17
/V
D
A
TA
6
N/
C
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0
ROM_OEn
ROM_WEn
ROM_CSn
CRVSS
CVDD_1.8
RESERVED
AVDD_LV_E_3.3
AVSS_LV_E
CH3P_LV_E/ER0
CH3N_LV_E/ER1
CLKP_LV_E/ER2
CLKN_LV_E/ER3
CH2P_LV_E/ER4
CH2N_LV_E/ER5
CH1P_LV_E/ER6
CH1N_LV_E/ER7
CH0P_LV_E/EG0
CH0N_LV_E/EG1
AVSS_LV_E
AVDD_LV_E_3..3
AVSS_LV
AVDD_LV_3.3
AVDD_LV_O_3.3
AVSS_LV_O
CH3P_LV_O/EG2
CH3N_LV_O/EG3
CLKP_LV_O/EG4
CLKN_LV_O/EG5
CH2P_LV_O/EG6
CH2N_LV_O/EG7
CH1P_LV_O/EB0
CH1N_LV_O/EB1
CH0P_LV_O/EB2
CH0N_LV_O/EB3
AVSS_LV_O
AVDD_LV_O_3..3
CVDD_1..8
CVSS
EB4
EB5
EB6
EB7
DEN
DHS
DVS
RVDD_3.3
CRVSS
N/C
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
10
1
10
2
10
3
10
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
AGND_ADC
RESERVED
AVDD_ADC_3.3
AGND_RED
RED-
RED+
AVDD_RED_3.3
AGND_GREEN
GREEN-
GREEN+
SOG_MCSS
AVDD_GREEN_3.3
AGND_BLUE
BLUE-
BLUE+
AVDD_BLUE_3.3
CRVSS
CVDD_1.8
RESERVED
VDD_RXPLL_1.8
GND_RXPLL
RESERVED
AVDD_RXC_3.3
RXC-
RXC+
AGND_RXC
AVDD_RX0_3.3
RX0-
RX0+
AGND_RX0
VDD_RX0_1.8
AVDD_RX1_3.3
RX1-
RX1+
AGND_RX1
VDD_RX1_1.8
AVDD_RX2_3.3
RX2-
RX2+
AGND_RX2
VDD_RX2_1.8
AGND_IMB
REXT
AVDD_IMB_3.3
VCLK
GPIO23/VDATA0
GPIO22/VDATA1
GPIO21/VDATA2
GPIO20/VDATA3
GPIO19/VDATA4
GPIO18/VDATA5
N/C
20
8
20
7
20
6
20
5
20
4
20
3
20
2
20
1
20
0
19
9
19
8
19
7
19
6
19
5
19
4
19
3
19
2
19
1
19
0
18
9
18
8
18
7
18
6
18
5
18
4
18
3
18
2
18
1
18
0
17
9
17
8
17
7
17
6
17
5
17
4
17
3
17
2
17
1
17
0
16
9
16
8
16
7
16
6
16
5
16
4
16
3
16
2
16
1
16
0
15
9
15
8
15
7
RO
M
_D
A
T
A
4
RO
M
_D
A
T
A
5
CRVSS
RVDD_
3.
3
RO
M
_D
A
T
A
6
RO
M
_D
A
T
A
7
RO
M
_ADDR
0
RO
M
_ADDR
1
RO
M
_ADDR
2
RO
M
_ADDR
3
RO
M
_ADDR
4
RO
M
_ADDR
5
RO
M
_ADDR
6
RO
M
_ADDR
7
RO
M
_ADDR
8
RO
M
_ADDR
9
RO
M
_ADDR
10
CRVSS
RVDD_
3.
3
RO
M
_ADDR
11
RO
M
_ADDR
12
RO
M
_ADDR
13
RO
M
_ADDR
14
RO
M
_ADDR
15
RO
M
_ADDR
16
RO
M
_ADDR
17
VS
YNC
HSY
N
C/C
S
YNC
CRVSS
CVDD_
1.
8
RES
ET
n
LBADC_
GND
LBADC_
RE
T
U
RN
LBADC_
IN3
LBADC_
IN2
LBADC_
IN1
LBADC_
V
D
D
_3
.3
AV
DD
_RPLL
_3
.3
TC
LK
XT
A
L
AGND
_RPLL
RES
ERVED
V
D
D
_RP
LL
_1
.8
G
ND_R
P
L
L
VDD_ADC_
1.
8
G
ND_ADC
N/
C
N/
C
N/
C
N/
C
N/
C
N/
C
Figure 2.
gm5221 Pin Out Diagram