Apalis Carrier Board Design Guide
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2.22.3 Unused Touch Panel Interface Signal Termination
If the touch panel interface is unused, either disable the corresponding driver or pull down the
signals individually with 10k
Ω
resistors.
2.23 Analogue Inputs
The Apalis modules feature up to four analogue input channels. The supported sampling rates and
resolutions depend on the modules. The input voltage span is from 0V to 3.3V. The ADC reference
is the analogue input voltage rail. The analogue input channels are not designed to be used for
high precision measurement tasks. The interface is intended to be used for battery voltage
monitoring (additional circuit required), ambient light sensors, simple analogue joystick input
devices, etc.
2.23.1 Analogue Input Signals
Apalis
Pin
Apalis
Signal Name
I/O
Type
Power
Rail
Description
305
AN1_ADC0
I
Analogue 3.3V
ADC input (3.3V max)
307
AN1_ADC1
I
Analogue 3.3V
ADC input (3.3V max)
309
AN1_ADC2
I
Analogue 3.3V
ADC input (3.3V max)
311
AN1_TSWIP_ADC3
I
Analogue 3.3V
ADC input (3.3V max), some modules might use this input for the
five wire resistive touch interface.
Table 35: Analogue Input Signals
2.23.2 Unused Analogue Inputs Signal Termination
The unused analogue input signals can be left unconnected or tied to the ground. It is
recommended to disable the corresponding inputs in the driver or disable the whole ADC block if
unused.
2.24 Clock Output
The Apalis standard reserves two module edge connector pins as clock outputs. One output is
intended to be used for the digital audio interface while the other can be used for the camera
interface. The clock outputs could also be used for other purposes if not required by the dedicated
function. Please note that on some modules, the possible output frequencies is limited. There might
also be limitations due to the other clock sources that are used in the module. Read carefully the
relevant datasheets.
2.24.1 Clock Output Signals
Apalis
Pin
Apalis
Signal Name
I/O
Type
Power
Rail
Description
194
DAP1_MCLK
O
Analogue 3.3V
Clock output for the digital audio interface
193
CAM1_MCLK
O
Analogue 3.3V
Clock output for the parallel and serial camera interface
Table 36: Clock Output Signals
2.24.2 Schematic and Layout Considerations
The clock output signals can have quite a high frequency, especially for single ended clock signals.
This could lead to major problems due to electromagnetic interferences (EMI). The clock signals
should be kept as short as possible. High slew rates of the signal can increase the EMI problems.
Therefore, it is desirable to reduce the slew rate as much as the signal quality allows it. Therefore,
series resistors should be placed close to the clock output of the module. Start with a value of 22
Ω
.
