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Toradex Apalis Series, Design Manual

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Apalis Carrier Board Design Guide 

Toradex AG  l  Altsagenstrasse 5  l  6048 Horw  l  Switzerland  l  +41 41 500 48 00  l  

www.toradex.com 

 l  

[email protected] 

Page | 25 

 

Figure 19: Fast Ethernet with integrated magnetics reference schematic  

2.4.3 

Unused Ethernet Signals Termination 

All unused Ethernet signals can be left unconnected.  

2.5  USB 

2.5.1 

USB Signals 

The Apalis standard features four USB interfaces. Two of them support the additional signals 
required for USB 3.0 SuperSpeed. One of the USB interfaces features the additional signals that 
are needed for OTG. The following table shows the possible features for each USB interface in the 
Apalis module standard. Please note that not every Apalis module will feature all the four USB 
interfaces or every USB feature. Please check the datasheet of the respective Apalis modules in 
order to determine which features are supported.  
 

Apalis Port 

1.5Mbit/s  
Low Speed  
(1.1) 

12 Mbit/s  
Full Speed  
(1.1) 

480Mbit/s  
High Speed  
(2.0) 

5Gbit/s  
SuperSpeed  
(3.0) 

OTG 

USBO1 

 

 

 

 

 

USBH2 

 

 

 

 

 

USBH3 

 

 

 

 

 

USBH4 

 

 

 

 

 

Table 8: Maximum possible supported features for the USB ports 

 
The USBO1 is a SuperSpeed OTG capable interface. As most Apalis modules will use this USB port 
for debugging and flash memory recovery, it is recommended that this interface is accessible even 
for carrier board designs which do not need any USB interface. This USB port does not share any 
signal with other ports and has its own power enable and overcurrent signals.  
 
The additional data links for USB 3.0 SuperSpeed run at 5 Gbit/s and are fully compliant with the 
PCI Express Base Specification, Revision 2.0. SuperSpeed signals support polarity inversion. This 
means the positive and negative signal pins can be inverted in order to simplify the layout by 

avoiding crossover of the signals. It is not permitted to swap the receiving signals with the 
transmitting ones. The USB 2.0 data signals do not support polarity inversion; D+ and D- cannot 
be swapped.  
 

 

ETH1_LINK_ACT

ETH1_SPEED

ETH1_TX0_N

ETH1_TX0_P

ETH1[0..6]

ETH1_RXI_P

ETH_RXI_N

3.3V_SW

3.3V_SW

150R

R2

150R

R1

J00-0065NL

TD+

1

TD-

2

CT_TXD

4

CT_RXD

5

RD+

3

RD-

6

LED_Left_A

9

LED_Left_C

10

LED_Right_C

11

LED_Right_A

12

SHIELD

S1

SHIELD

S2

NC

7

CHS GND

8

X2

ETH1_TX0_P

ETH1_RXI_N

ETH1_RXI_P

SHIELD2

MM70-314-310B1

ET

50

Apalis - Gigabit Ethernet

2 of 25

ETH1_MDI0-

48

ET

56

ETH1_MDI1-

54

ET

32

ETH1_MDI2-

34

ET

38

ETH1_MDI3-

40

ETH1_ACT

42

ETH1_LINK

44

ETH1_CTREF

46

X1B

ETH1_TX0_N

ETH1_LINK_ACT
ETH1_SPEED

100nF

16V

C3

100nF

16V

C4

2A

220R@100MHz

L1

GND

ETH1_CTREF

ETH1_CTREF_TXD

ETH1_CTREF_RXD

100nF

16V

C2

0R

R3

0R

R4

GND

GND

ETH1_CTREF_ALL

47uF

6.3V

+C1

GND

ETH1_CTREF_TXD

ETH1_CTREF_RXD

ETH1_CTREF

NA

NA

NA

NA

NA

Summary of Contents for Apalis Series

Page 1: ...Apalis Computer Module Carrier Board Design Guide ...

Page 2: ...on 3 5 add information about current consumption budget 16 June 2016 V1 5 Section 2 1 1 update information about preferred interfaces Section 2 12 add recommendation using MMC1 instead of SD1 as preferred interface Section 0 add suitable spacer Add information about CSI DSI and recovery mode 29 June 2016 V1 6 Section 2 5 2 1 Add information about incompatible USB 3 0 OTG cables 09 October 2018 V1 ...

Page 3: ...ce Schematics 22 2 4 3 Unused Ethernet Signals Termination 25 2 5 USB 25 2 5 1 USB Signals 25 2 5 2 Reference Schematics 27 2 5 3 Unused USB Signal Termination 32 2 6 Parallel RGB LCD Interface 33 2 6 1 Parallel RGB LCD Signals 33 2 6 2 Color Mapping 34 2 6 3 Reference Schematics 35 2 6 4 Unused Parallel RGB Interface Signal Termination 37 2 7 LVDS LCD Interface 38 2 7 1 LVDS Signals 38 2 7 2 Comp...

Page 4: ...used Analogue Audio Signal Termination 57 2 20 Digital Audio 57 2 20 1 Digital Audio Signals 57 2 20 2 Reference Schematics 57 2 20 3 Unused Digital Audio Interface Signal Termination 58 2 21 S PDIF Sony Philips Digital Interface I O 58 2 21 1 S PDIF Signals 58 2 21 2 Reference Schematics 58 2 21 3 Unused S PDIF Interface Signal Termination 59 2 22 Touch Panel Interface 59 2 22 1 Resistive Touch S...

Page 5: ...oradex com Page 5 3 5 Reference Schematics 69 4 Mechanical and Thermal Consideration 71 4 1 Module Connector 71 4 2 Fixation of the Module 71 4 3 Thermal Solution 73 4 4 Module Size 74 4 5 Connector and MXM SnapLock Land Pattern Requirements 75 4 6 Carrier Board Space Requirements 76 5 Appendix A Physical Pin Definition and Location 79 ...

Page 6: ...formation to the routing of these interfaces 1 2 Additional Documents 1 2 1 Layout Design Guide This document contains layout requirement specifications for the high speed signals and helps to avoid problems related with the layout http developer toradex com hardware resources arm family carrier board design 1 2 2 Apalis Module Datasheets For every Apalis Module there is a datasheet available Amon...

Page 7: ...in this document DDC2B based on I2 C is always meant DRC Design Rule Check a tool for checking whether all design rules are satisfied in a CAD tool DSI Display Serial Interface DVI Digital Visual Interface digital signals are electrical compatible with HDMI DVI A Digital Visual Interface Analogue only signals are compatible with VGA DVI D Digital Visual Interface Digital only signals are electrica...

Page 8: ...nted Circuit Board PCI Peripheral Component Interconnect parallel computer expansion bus for connecting peripherals PCIe PCI Express high speed serial computer expansion bus replaces the PCI bus PCM Pulse Code Modulation digitally representation of analogue signals standard interface for digital audio PD Pull Down Resistor PHY Physical Layer of the OSI model PMIC Power Management IC integrated cir...

Page 9: ... Explanation UART Universal Asynchronous Receiver Transmitter serial interface in combination with a transceiver a RS232 RS422 RS485 IrDA or similar interface can be achieved USB Universal Serial Bus serial interface for internal and external peripherals VCC Positive supply voltage VGA Video Graphics Array analogue video interface for monitors Table 1 Abbreviations ...

Page 10: ...functionally or electrically compatible between modules If a carrier board design uses such interfaces then it is possible that other modules in the Apalis module family do not provide these interfaces and instead provide another interface on the associated pins These interfaces might be electrically incompatible In this case the carrier board will be restricted for use only with certain Apalis mo...

Page 11: ...th Apalis modules that do not feature all UART ports Special attention should be taken to the USB ports Since only USBO1 and USBH4 are SuperSpeed capable The Apalis TK1 provides USBO1 USBH2 and USBH4 while USBH3 is left unconnected On the other hand Apalis T30 provides USBO1 USBH2 and USBH3 while USBH4 is unconnected Carrier board designs which require 3 USB interfaces may need assembly option for...

Page 12: ... specific interface then they shall be assigned to the same pins in the type specific area of the connector Hence both module A and module B shall share compatibility between these parts of the type specific interface The signal routing and need for external components for the type specific interfaces are not reflected in this document Please consult the applicable Apalis module datasheet for more...

Page 13: ... 37 WAKE1_MICO I CMOS 3 3V General purpose wake signal 26 RESET_MOCI O CMOS 3 3V General reset output of the module 209 I2C1_SDA I O OD 3 3V I2C interface data some PICe device need SMB interface for special configuration 211 I2C1_SCL O OD 3 3V I2C interface clock some PICe device need SMB interface for special configuration Table 3 PCIe signals The PCIe interface supports polarity inversion This ...

Page 14: ...ch is used or the PCIe interfaces in the type specific area do not provide additional clock outputs a zero delay PCIe clock buffer is required on the baseboard Some PCIe switches features an internal PCIe clock buffer which can avoid the necessity of a dedicated clock buffer Figure 5 PCIe reference clock buffer example 2 2 2 1 PCIe x1 Slot Schematic Example The PCIe card slot design defines that t...

Page 15: ...al to wake up the module from its suspend state The JTAG interface on the PCIe slot can be left unconnected This interface is only used for debugging purposes No termination on the carrier board is needed The PCIe slot pin out features an SMB interface for additional power management control As the SMB and I2C buses are compatible it is recommended that the I2C1 interface on the Apalis module is u...

Page 16: ...uch as reset and hot plug detect as secondary functions or as type specific interfaces Nevertheless as compatibility between different Apalis modules could PRSNT1 A1 12V B1 12V A2 12V B2 12V A3 RSVD B3 GND A4 GND B4 TCK A5 SMCLK B5 TDI A6 SMDAT B6 TDO A7 GND B7 TMS A8 3 3V B8 3 3V A9 TRST B9 3 3V A10 3 3VAux B10 PERST A11 WAKE B11 GND A12 RSVD B12 REFCLK A13 GND B13 REFCLK A14 PET0 B14 GND A15 PET...

Page 17: ...CIe_TX 31 PCIe_TX 33 GND 35 GND 37 RSVD 39 RSVD 41 GND 43 RSVD 45 RSVD 47 RSVD 49 RSVD 51 UIM_CLOCK 12 UIM_RESET 14 UIM_VPP 16 GND 18 W_DISABLE 20 PERST 22 3V3_AUX 24 GND 26 1V5 28 SMB_CLK 30 SMB_DAT 32 GND 34 USB_D 36 USB_D 38 GND 40 LED_WWAN 42 LED_WLAN 44 LED_WPAN 46 1V5 48 GND 50 3V3 52 X2 7111S2015X02LF VCC 1 RESET 2 CLOCK 3 GND 5 VPP 6 I O 7 X3 SC4215A NC 1 EN 2 V_IN 3 NC 4 NC 5 V_OUT 6 FB 7...

Page 18: ...3P3_2 27 VDD3P3_3 41 VDD3P3_4 51 VDD3P3_5 64 VDD1P5_1 47 VDD1P5_2 56 VDD0P9_1 11 VDD0P9_2 32 VDD0P9_3 42 VDD0P9_4 59 RSVD_22_NC 22 VDD1P5_OUT 39 VDD0P9_OUT 40 CTOP 40 CBOT 37 GND HS IC1B PCIE1_RX_N PCIE1_RX_P PCIE1_TX_N PCIE1_TX_P PCIE1_CLK_N PCIE1_CLK_P PCIE1_RX_S_N PCIE1_RX_S_P PCIE1_TX_N PCIE1_TX_P PCIE1_CLK_N PCIE1_CLK_P PCIE1 0 5 100nF C1 100nF C2 PCIE1_RX_N PCIE1_RX_P SYSTEM_CTRL 0 1 MM70 31...

Page 19: ...alis Pin Apalis Signal Name I O Type Power Rail Description 33 SATA1_TX O SATA SATA transmit data positive 31 SATA1_TX O SATA SATA transmit data negative 25 SATA1_RX I SATA SATA receive data positive 27 SATA1_RX I SATA SATA receive data negative 35 SATA1_ACT O OD 3 3V Activity indication LED output active low Table 5 SATA Signals The SATA interface does not support polarity inversion This means th...

Page 20: ... the SATA interface instead Even though the pin out of the mSATA seems to be similar to the Mini PCIe Card there is an important pitfall to remark Officially the Mini PCIe Card features the RX signal on pin 25 and RX on pin 23 The mSATA interface specifies the RX signal on pin 23 and RX signal on 25 The PCIe interface supports polarity reversal but not the SATA interface This means that additional...

Page 21: ..._TX SATA1_TX SATA1_RX SATA1_RX 2x 10nF 2x 10nF mSATA Slot Connector Mini PCIe Card HSOp 0 HSOn 0 HSIp 0 HSIn 0 MM70 314 310B1 Apalis SATA 19 of 25 SATA1_RX 27 SATA1_RX 25 SATA1_TX 31 SATA1_TX 33 SATA1_ACT 35 X1S SATA1_RX_P SATA1_TX_N SATA1_TX_P SATA1_RX_N Mini PCIe Latch MECH1 67910 5700 WAKE 1 3V3 2 COEX1 3 GND 4 COEX2 5 1V5 6 CLKREQ 7 UIM_PWR 8 GND 9 UIM_DATA 10 REF_CLK 11 REF_CLK 13 GND 15 SIM_...

Page 22: ...32 ETH1_MDI2 I O Analogue 1000Base T DC 10 100Base TX Unused 34 ETH1_MDI2 I O Analogue 1000Base T DC 10 100Base TX Unused 38 ETH1_MDI3 I O Analogue 1000Base T DD 10 100Base TX Unused 40 ETH1_MDI3 I O Analogue 1000Base T DD 10 100Base TX Unused 46 ETH _CTREF O Analogue Centre tap supply 42 ETH1_ACT O CMOS 3 3V LED indication output for activity on the Ethernet port 44 ETH1_LINK O CMOS 3 3V LED indi...

Page 23: ...e isolated from the other signals It is therefore necessary to place a dedicated ground plane under these signals which has a minimum separation of 2mm from every other signal and plane Additionally a separate shield ground for the LAN device is needed Try to place the magnetics as close as possible to the Ethernet jack This reduces the length of the signal traces between the magnetics and jack 10...

Page 24: ...Hz L1 GND 150R R6 150R R5 SHIELD MM70 314 310B1 ETH1_MDI0 50 Apalis Gigabit Ethernet 2 of 25 ETH1_MDI0 48 ETH1_MDI1 56 ETH1_MDI1 54 ETH1_MDI2 32 ETH1_MDI2 34 ETH1_MDI3 38 ETH1_MDI3 40 ETH1_ACT 42 ETH1_LINK 44 ETH1_CTREF 46 X1B ETH1_MDI0_N ETH1_MDI1_P ETH1_MDI1_N ETH1_MDI2_P ETH1_MDI2_N ETH1_MDI3_P ETH1_MDI3_N ETH1_MDI0_P ETH1_ACT ETH1_LINK ETH1_CTREF ETH1_MDI0_N ETH1_MDI1_P ETH1_MDI1_N ETH1_MDI2_P...

Page 25: ...this interface is accessible even for carrier board designs which do not need any USB interface This USB port does not share any signal with other ports and has its own power enable and overcurrent signals The additional data links for USB 3 0 SuperSpeed run at 5 Gbit s and are fully compliant with the PCI Express Base Specification Revision 2 0 SuperSpeed signals support polarity inversion This m...

Page 26: ...I O Type Power Rail Description 80 USBH2_D I O USB 3 3V Positive differential USB host signal 82 USBH2_D I O USB 3 3V Negative differential USB host signal 84 USBH_EN O CMOS 3 3V Enable signal for the bus voltage output shared with all USB host ports 96 USBH_OC I OD 3 3V Over current input signal shared with all USB host ports Table 10 USBH2 signals Apalis Pin Apalis Signal Name I O Type Power Rai...

Page 27: ... The USB 2 0 data signals do not need any series capacitors at all If the USB signals are externally available ESD protection diodes need to be placed on all of the USB signals Make sure that the protection diodes are USB 3 0 compliant The USB 2 0 signals additionally require a common mode choke for passing EMI testing Use common mode chokes that are specified for High speed USB 2 0 Figure 20 USB ...

Page 28: ...d TX lines These cables are not compatible with the reference schematic Only OTG cables that are not crossing the SuperSpeed signals are compatible The non compatible adapter cables often are promoted as OTG cables for the Samsung Galaxy Note 3 cellphone The Micro A plug of these cables also have a wrong shape They are shaped as Micro B plug even though it is a Micro A plug 2 5 2 2 USB 2 0 Client ...

Page 29: ...s a USB 3 0 host interface As USB 3 0 is backward compatible this port could also be used as a USB 2 0 host interface Apalis Module Carrier Board TX RX USBO1_SSTX USBO1_SSTX USBO1_SSRX USBO1_SSRX 2x 100nF USBO1_D USBO1_D USBO1_D USBO1_D RX TX USB 3 0 OTG Controller Super Speed USB 2 0 1 1 Module Connector USB 2 0 Connector D D USB 2 0 Host USB 2 0 1 1 RX TX USB 2 0 Connector USB Drive USB Cable TV...

Page 30: ...s resistors can be added for reducing the Apalis Module Carrier Board TX RX RX TX USBH4_SSTX USBH4_SSTX USBH4_SSRX USBH4_SSRX USBH4_SSTX USBH4_SSTX USBH4_SSRX USBH4_SSRX 2x 100nF 2x 100nF SSTX SSTX SSRX SSRX USBH4_D USBH4_D USBH4_D USBH4_D RX TX USB 3 0 Host Super Speed USB 2 0 1 1 Module Connector USB 3 0 Connector D D USB 3 0 Device Super Speed USB 2 0 1 1 RX TX USB 3 0 Connector USB Drive USB C...

Page 31: ...X_P USBH4_SSRX_N USBH4_SSRX_P TUSB9261 PWM0 2 PWM1 3 GRSTz 4 GPIO8 UART_RX 5 GPIO9 UART_TX 6 GPIO0 8 GPIO1 9 GPIO2 10 GPIO3 11 GPIO4 13 GPIO5 14 GPIO6 15 GPIO7 16 SPI_SCLK 17 SPI_DATA_OUT 18 SPI_DATA_IN 20 SPI_CS0 21 SPI_CS1 GPIO10 22 SPI_CS2 GPIO11 23 JTAG_TCK 25 JTAG_TDI 26 JTAG_TDO 27 JTAG_TMS 28 JTAG_TRSTz 29 FREQSEL0 30 FREQSEL1 31 USB_DM 35 USB_DP 36 NC 37 USB_R1 38 USB_R1RTN 39 USB_SSTXM 42...

Page 32: ...sed 86 USBH3_D Leave NC if not used 88 USBH3_D Leave NC if not used 98 USBH4_D Leave NC if not used 100 USBH4_D Leave NC if not used 94 USB H4_SSRX Leave NC if not used 92 USB H4_SSRX Leave NC if not used 106 USBH4_SSTX Leave NC if not used 104 USB H4_SSTX Leave NC if not used 72 USBO1_ID Leave NC and set the USB port direction in software to host or client OR ground the pin if port is used perman...

Page 33: ...3V 273 LCD1_G2 O CMOS 3 3V 275 LCD1_G3 O CMOS 3 3V 277 LCD1_G4 O CMOS 3 3V 279 LCD1_G5 O CMOS 3 3V 281 LCD1_G6 O CMOS 3 3V 283 LCD1_G7 O CMOS 3 3V 287 LCD1_B0 O CMOS 3 3V Blue LCD data signals LSB 0 MSB 7 289 LCD1_B1 O CMOS 3 3V 291 LCD1_B2 O CMOS 3 3V 293 LCD1_B3 O CMOS 3 3V 295 LCD1_B4 O CMOS 3 3V 297 LCD1_B5 O CMOS 3 3V 299 LCD1_B6 O CMOS 3 3V 301 LCD1_B7 O CMOS 3 3V 249 LCD1_DE O CMOS 3 3V Dat...

Page 34: ...s for this configuration Some Apalis Modules might feature additional color mappings for 18 or 16 bit displays These mappings might be incompatible with the 24 bit mapping of the Apalis standard In order to keep the design compatible it is recommended to attach 18 or 16 bit displays to the 24 bit mapped interface as the following table shows Apalis Pin Apalis Signal Name 24 bit RGB 18 bit RGB 16 b...

Page 35: ...6 LCD1_B7 LCD1_B2 LCD1_B3 LCD1_B4 LCD1_B5 LCD1_DE LCD1_R7 LCD1_R6 PWM_BKL1 BKL1_ON 3 3V_SW LCD1_B1 LCD1_B0 LCD1_G0 LCD1_G1 LCD1_R0 LCD1_R1 PCA9306DCTT GND 1 VREF1 2 SCL1 3 EN 8 SDA1 4 SDA2 5 SCL2 6 VREF2 7 IC1 GND R31 100K 100nF 16V C2 GND R33 1 8K R32 1 8K 500mA 220R 100MHz L1 500mA 220R 100MHz L2 4 7pF C4 4 7pF C3 R35 1 8K R34 1 8K GND I2C2_SCL I2C2_SDA I2C2_DDC_SDA_C I2C2_DDC_SCL_C 100nF 16V C1...

Page 36: ... GND 47pF 50V C22 GND 500mA 220R 100MHz L7 SN74LVC1G17 NC 1 A 2 GND 3 Y 4 VCC 5 IC4 5V_SW 33R R45 100nF 16V C23 RCLAMP0504S D2 SHIELD2 RCLAMP0504S D1 10pF 50V C7 10pF 50V C8 GND 600mA 40R 100MHz L3 10pF 50V C9 10pF 50V C10 GND 600mA 40R 100MHz L4 10pF 50V C11 10pF 50V C12 GND 600mA 40R 100MHz L5 GND GND GND GND GND GND GND GND GND GND GND GND GND GND SHIELD2 75R R15 75R R21 75R R28 MXM3_243 MXM3_2...

Page 37: ...VDS2 36 GND LVDS3 31 2 of 2 IC4B R33 1K VCC_LVDS VCC_PLL GND LVDS1 0 7 3 3V_LVDS1 100nF 16V C51 GND DF13A 20DP 1 25v 56 VCC_5V 1 VCC_LVDS 2 3 6 LVDS_OUT0 5 LVDS_OUT0 7 18 LVDS_OUT1 8 LVDS_OUT1 10 9 LVDS_OUT2 11 LVDS_OUT2 13 12 LVDS_CLK 14 LVDS_CLK 16 15 BL ON 17 BL CTRL 4 SEL1 19 SEL2 20 X18 LVDS1_CLK_N LVDS1_CLK_P LVDS1_OUT0_N LVDS1_OUT0_P LVDS1_OUT1_N LVDS1_OUT1_P LVDS1_OUT2_N LVDS1_OUT2_P 2A 22...

Page 38: ... 288 LVDS1_B_TX1 O LVDS LVDS data lane 1 for channel B odd pixels unused for single channel 290 LVDS1_B_TX1 O LVDS 294 LVDS1_B_TX2 O LVDS LVDS data lane 2 for channel B odd pixels unused for single channel 296 LVDS1_B_TX2 O LVDS 300 LVDS1_B_TX3 O LVDS LVDS data lane 3 for channel B odd pixels unused for single channel unused for 18 bit 302 LVDS1_B_TX3 O LVDS 239 BKL1_PWM O CMOS 3 3V Backlight PWM ...

Page 39: ...in Dual Channel Mode TX0 Single Channel Display TX1 TX2 TX3 RX0 RX1 RX2 CLK CLK TX0 TX1 TX2 TX3 CLK RX3 Transmitter in Dual Channel Mode TX0 Dual Channel Display TX1 TX2 TX3 RX0 RX1 RX2 CLK CLK TX0 TX1 TX2 TX3 RX0 RX1 RX2 CLK CLK RX3 RX3 18bit Transmitter TX0 18bit Display TX1 TX2 RX0 RX1 RX2 CLK CLK 18bit Transmitter TX0 24bit JEIDA Display TX1 TX2 RX0 RX1 RX2 RX3 CLK CLK 18bit Transmitter TX0 24...

Page 40: ...Most of the 24 bit LVDS displays follow the VESA Color mapping The VESA color mapping does not rename the signal bits This means that the position of the MSB is different as they are available in the additional data pair Hence the VESA color mapping is not compatible with the 18 bit interface Figure 37 24 bit VESA LVDS color mapping LVDS1_A_CLK LVDS1_B_CLK LVDS1_A_TX0 LVDS1_B_TX0 LVDS1_A_TX1 LVDS1...

Page 41: ...1O LVDS1_A_CLK_N LVDS1_A_CLK_P LVDS1_A_TX0_N LVDS1_A_TX0_P LVDS1_A_TX1_N LVDS1_A_TX1_P LVDS1_A_TX2_N LVDS1_A_TX2_P LVDS1_A_TX3_N LVDS1_A_TX3_P LVDS1_B_CLK_N LVDS1_B_CLK_P LVDS1_B_TX0_N LVDS1_B_TX0_P LVDS1_B_TX1_N LVDS1_B_TX1_P LVDS1_B_TX2_N LVDS1_B_TX2_P LVDS1_B_TX3_N LVDS1_B_TX3_P DF13A 40DP 1 25v 55 GND 2 GND 5 GND 17 GND 8 GND 11 GND 14 1 25mm pitch Connector LVDS1_A_CLK 27 LVDS1_A_CLK 25 LVDS1...

Page 42: ...er DDC This interface is shared with other display interfaces 207 I2C2_SCL O OD 3 3V Table 17 HDMI DVI signals 2 8 2 Reference Schematics 2 8 2 1 DVI Schematic Example There are different DVI connector configurations available The DVI D digital supports only the native DVI signals The DVI A analogue provides only analogue VGA signals The DVI I integrated combines the digital DVI signals and the an...

Page 43: ...I 24 of 25 HDMI1_TXC 242 HDMI1_TXC 240 HDMI1_TXD0 236 HDMI1_TXD0 234 HDMI1_HPD 232 HDMI1_TXD1 230 HDMI1_TXD1 228 HDMI1_TXD2 224 HDMI1_TXD2 222 X1X HDMI1_HPD HDMI1_HPD HDMI1_TXC_N HDMI1_TXC_P HDMI1_TXD0_N HDMI1_TXD0_P HDMI1_TXD1_N HDMI1_TXD1_P HDMI1_TXD2_N HDMI1_TXD2_P RCLAMP0504S D2 SHIELD RCLAMP0504S D3 SHIELD HDMI1_TXC_N HDMI1_TXC_P HDMI1_TXD0_N HDMI1_TXD0_P HDMI1_TXD1_N HDMI1_TXD1_P HDMI1_TXD2_...

Page 44: ...lay identification data EDID over DDC This interface is shared with other display interfaces 207 I2C2_SCL O OD 3 3V Table 19 VGA signals HDMI1_HPD_MXM3 10K R3 220pF 50V C2 GND PLACE D1 D2 D3 NEAR THE DVI I CONNECTOR SHIELD MM70 314 310B1 HDMI1_CEC 220 Apalis HDMI 24 of 25 HDMI1_TXC 242 HDMI1_TXC 240 HDMI1_TXD0 236 HDMI1_TXD0 234 HDMI1_HPD 232 HDMI1_TXD1 230 HDMI1_TXD1 228 HDMI1_TXD2 224 HDMI1_TXD2...

Page 45: ...rface signals can be left unconnected 2 10 Display Serial Interface MIPI DSI The MIPI DSI interface is not a standard interface in the Apalis module family If a module features DSI the according signals are located in the type specific area of the MXM3 module edge connector Toradex tries to keep the position of the signals compatible between the different modules but as it is not a standard interf...

Page 46: ...SCL O OD 3 3V Table 20 Parallel Camera Signals 2 11 2 Unused Parallel Camera Interface Signal Termination All unused parallel camera input signals can be left unconnected if the interface is disabled in software These signals may be able to be used as GPIOs when they are not used as camera interface Please consult the applicable Apalis module datasheet 2 12 Camera Serial Interface MIPI CSI 2 The M...

Page 47: ...y It is the preferred solution Even if the external pull up resistors are not mandatory we recommend adding unassembled pull up resistors to the 3 3V rail in order for it to be compatible with the future modules Bus Speed Mode Max Clock Frequency Max Bus Speed Signal Voltage Default Speed 25 MHz 12 5 MB s 3 3V High Speed 50 MHz 25 MB s 3 3V SDR12 25 MHz 12 5 MB s 1 8V SDR25 50 MHz 25 MB s 1 8V DDR...

Page 48: ...rder to do a full reset of the controller in the SD card Most cards do not require this procedure and work perfectly without a power switching feature For switching the card power rail any free GPIO can be used However if the MMC1_D4 pin 148 is used the latest Toradex BSP works without need for modifications Figure 42 4bit SD Card Slot Reference Schematic 2 13 2 2 MMC Card Slot 8bit Reference Sche...

Page 49: ... O OD 3 3V Display Data Channel I2 C data signal pull up resistor required on carrier board 207 I2C2_SCL O OD 3 3V Display Data Channel I2 C clock signal pull up resistor required on carrier board 201 I2C3_SDA I O OD 3 3V Camera interface I2 C data signal pull up resistor required on carrier board 203 I2C3_SCL O OD 3 3V Camera interface I2 C clock signal pull up resistor required on carrier board ...

Page 50: ...es might provide additional flow control signals on non standard pins 2 15 1 UART Signals Apalis Pin Apalis Signal Name I O Type Power Rail Description 118 UART1_RXD I CMOS 3 3V Received Data 112 UART1_TXD O CMOS 3 3V Transmitted Data 114 UART1_RTS O CMOS 3 3V Request to Send 116 UART1_CTS I CMOS 3 3V Clear to Send 110 UART1_DTR O CMOS 3 3V Data Terminal Ready 120 UART1_DSR I CMOS 3 3V Data Set Re...

Page 51: ...RS422 has separate RX and TX signal pairs no additional control signals are required for changing the signal direction This means the RS422 requires only the RX and TX signals of the UART interface Therefore it is possible to use any of the four standard UART interfaces of the Apalis standard The RS422 specification does not contain a connector Therefore there is no standard connector for this int...

Page 52: ...out compared to some peripheral devices Figure 47 RS485 Reference Schematic 2 15 2 4 IrDA Reference Schematics IrDA is an optical wireless communication interface There are different physical layer modulation schemes available Make sure that you check which modes are supported by a specific Apalis module and the peripheral devices ADM3491ARZ Rx 12 Rx 11 Tx 10 Tx 9 NC 1 RO 2 nRE 3 DE 4 DI 5 GND 6 G...

Page 53: ... it at the negative edge The SPI modes describe these different behaviors Make sure that the relevant Apalis module and the peripheral devices are set to the same SPI mode SPI Mode Clock Polarity Clock Phase Description 0 0 0 Clock has positive polarity and the data is latched at the positive edge of SCK 1 0 1 Clock has positive polarity and the data is latched at the negative edge of SCK 2 1 0 Cl...

Page 54: ...ti master serial bus standard It was first introduced for the automotive sector and soon became widely adopted in the industrial sector Different versions of CAN specifications are available Make sure that the corresponding Apalis module complies with the required version 2 17 1 CAN Signals Apalis Pin Apalis Signal Name I O Type Power Rail Description 14 CAN1_TX O CMOS 3 3V CAN port 1 transmit pin...

Page 55: ...teps can also vary between the different Apalis modules 2 18 1 PWM Signals Apalis Pin Apalis Signal Name I O Type Power Rail Description 2 PWM1 O CMOS 3 3V General purpose PWM output 4 PWM2 O CMOS 3 3V General purpose PWM output 6 PWM3 O CMOS 3 3V General purpose PWM output 8 PWM4 O CMOS 3 3V General purpose PWM output 239 BKL1_PWM O CMOS 3 3V Dedicated PWM output for the LCD display backlight Tab...

Page 56: ...nes larger capacitors 47µF and more are recommended The line in and microphone signals do not require serial capacitors since they are already placed on the module Some microphones e g the widely used electret microphones require a phantom power The reference schematic below shows a suitable solution for common electret microphone capsules Please note that some microphones require that the phantom...

Page 57: ...lect 200 DAP1_BIT_CLK O CMOS 3 3V Serial bit clock 194 DAP1_MCLK O CMOS 3 3V External Peripheral Clock Table 32 Digital Audio Signals 2 20 2 Reference Schematics The supported audio codec interface standards vary between the modules The following reference schematic shows the implementation of a HDA codec Carefully check the direction of the signals For example the Realtek ALC889 HDA audio codec n...

Page 58: ..._SYNC DAP1_BIT_CLK DAP1_RESET DAP1_3 3V_DV DAP1_5V_AV 10uF 6 3V C252 100nF 16V C251 1uF 16V C250 GND GND DAP1_HDA_SIDESURROUND_R DAP1_HDA_SIDESURROUND_L DAP1_HDA_LOW_FREQ DAP1_HDA_CENTER DAP1_HDA_MIC2_R DAP1_HDA_MIC2_VREF DAP1_HDA_MIC2_L DAP1_HDA_LINE2_R DAP1_HDA_LINE2_VREF DAP1_HDA_LINE2_L DAP1_HDA_FRONT_R DAP1_HDA_FRONT_L DAP1_HDA_LINE1_R DAP1_HDA_LINE1_VREF DAP1_HDA_LINE1_L DAP1_HDA_MIC1_VREF_R...

Page 59: ...22 2 Reference Schematics In order to reduce noise that is picked up by the display or long cables it is recommended to add capacitor to the touch screen signals 1nF to 10nF is a good choice It is also recommended to add clamping diodes in order to protect the input of the touch screen controller against ESD Figure 54 Touch Interface Reference Schematic MM70 314 310B1 Apalis SPDIF 13 of 25 SPDIF1_...

Page 60: ...nalogue input signals can be left unconnected or tied to the ground It is recommended to disable the corresponding inputs in the driver or disable the whole ADC block if unused 2 24 Clock Output The Apalis standard reserves two module edge connector pins as clock outputs One output is intended to be used for the digital audio interface while the other can be used for the camera interface The clock...

Page 61: ...ew of the interfaces Some interfaces are stated as GPIO Capable This means all Apalis modules shall provide GPIO functionality on these pins as secondary function The interfaces that are listed as optional GPIO capable may be compatible on some modules For carrier board designs that provide the highest compatibility with all Apalis modules it is recommended to use the 8 dedicated GPIO signals firs...

Page 62: ...very The module recovery is required if the bootloader on the is no longer capable of booting the module In the normal software update process this feature is not required The procedure of recover a module depends on the module There is no common process Therefore it is necessary to consult the according module datasheet for more information to the hardware requirements ...

Page 63: ...upply is used on the module for the analogue circuits 3 3V needs to be provided to this input even if the analogue interfaces are not used in the design In this case the pins can be connected to the 3 3V digital supply for the module For a better audio quality and improved resistive touch performance it is recommended that separate filters are added to the analogue power supply rail For the best q...

Page 64: ...d peripherals are active These are just the standard power state If additional power saving is necessary it is possible to introduce other states in which some of the carrier board peripherals are switched off In this case free GPIO can be used to switch off unused peripheral power rails 7 24V Enable Enable PWR_OK Module 3 3V RTC RESET_MICO RESET_MOCI POWER_ENABLE_MOCI WAKE1_MICO 5V Analog Circuit...

Page 65: ... figure shows a sequence diagram for the different power states The module automatically enters into the running mode when the main power rail is applied to the module In the running mode the system can be set to a suspend state by the software There might be different wake up sources available Consult the datasheet for a specific Apalis module for more information about the available wakeup event...

Page 66: ...at least 100ms before releasing the reset The Apalis modules guarantees to apply the reset output RESET_MOCI not earlier than 120ms after the POWER_ENABLE_MOCI goes high This gives the carrier board a maximum time of 20ms for ramping up all power rails Some Apalis module might have longer delay but in order to be compatible with all Apalis modules count on the previous stated numbers Figure 57 Pow...

Page 67: ...d the module starts booting again This guarantees a minimum reset time of 1ms even if the reset input RESET_MICO is triggered for a short time Some Apalis modules may implement a power cycle during reset Figure 59 Reset sequence 7 27V Carrier Board in VCC input for Module Module internal Rails POWER_ENABLE_MOCI 5V for Perpherals on CB 3 3V for Perpherals on CB RESET_MOCI WAKE1_MICO Shut Down RUN O...

Page 68: ...E1_MICO If peripheral voltage rails are switched off by GPIO signals make sure that the ramping up of the voltages follows the requirement Figure 61 Resume from suspend sequence 7 27V Carrier Board in VCC input for Module Module internal Rails POWER_ENABLE_MOCI 5V for Perpherals on CB 3 3V for Perpherals on CB RESET_MOCI WAKE1_MICO Suspend RUN SUS State SUS RUN SUS RUN Module internal Reset RESET_...

Page 69: ...istor can be optionally placed on the carrier board on the POWER_ENABLE_MOCI signal This pull up resistor is only needed to prevent unwanted enabling of the peripheral voltages if the module is not inserted For designs in which the module is never removed this pull up is not required A 100kΩ resistor is recommended The RESET_MICO and RESET_MOCI do not need any pull up resistors on the carrier boar...

Page 70: ... 50V C8 10uF 50V C9 10uF 50V C2 10uF 50V C1 8 2uH 6 25A L20 4 7uH 6 2A L21 V5FILT R157 3 3K R156 3 6K V5FILT 150uF 10V C3 150uF 10V C4 150uF 10V C5 1nF 50V C74 Power Supply Controller DMP2022LSS 13 3 2 1 4 5 6 7 8 T3 3 3V 3 3V_SW 150uF 10V C10 150uF 10V C11 150uF 10V C12 SI 1024 X 2 1 6 T4A GND R3 100K 10nF 25V C13 R4 100K 5V_PGOOD 3 3V_SW_EN 3 3V_SW_EN_R SI 1024 X 3 5 4 T4B NA NA NA NA 10uF 50V C...

Page 71: ...ht is too small Components on bottom can be up to 1 8mm ACES 91782 314xx xxx 5mm Different position of alignment post SnapLock not possible for this spacer height Module needs to be screwed down Attend 125B 78C00 5mm Different position of alignment post SnapLock not possible for this spacer height Module needs to be screwed down Foxconn AS0B826 S43B 7H 1 5mm Different position of alignment post No...

Page 72: ...acers are soldered while the spacers used on the evaluation board are press fitted Therefore the required PCB footprint is slightly different Please read the according Würth datasheet During the development process it may be necessary to replace the module several times Screwing the module to the carrier board during development can be very inconvenient The Apalis module standard defines a mechani...

Page 73: ...ng solution Passive means that the natural convection is used to transport the heat from the surface to the air The efficiency of the natural convection is dependent on the housings and the environment but it has no moving parts and does not produce additional noise If the passive cooling is not sufficient a fan can be mounted on top of the heat sink This increases the efficiency dramatically In o...

Page 74: ... have a height of 3mm Figure 71 Stacking height of heat sink 4 4 Module Size Figure 72 Module dimension top side dimensions in mm On the bottom side all modules feature a pad with a diameter of 6mm in the middle of the PCB A standoff placed on the carrier board that connects with this location supports the module if the cooling solution applies force At both edges of the module ten test pads are a...

Page 75: ... module SnapLock and spacers with screws but must implement one of them The pad and hole sizes for the standoffs depends on the assembled parts Contact the supplier of the standoff in order to get the land pattern requirements Figure 74 SnapLock and standoff land pattern dimensions in mm The proposed land pattern of the MXM3 module connector is slightly different form the one that can be found in ...

Page 76: ...re shows the maximum required area if the SnapLock is used in combination with the suitable Toradex heat sink Custom heat sink solutions might need additional space on the carrier board Figure 76 Maximum carrier board space requirement dimensions in mm If a system does not need a cooling solution and the module is fixed by screwing it down the required carrier board area becomes smaller 2 95 3 30 ...

Page 77: ...Apalis module needs to be considered The following figure shows the maximum occupied volume at the bottom side of the Apalis module Figure 78 Maximum space requirement of components on module bottom view On the bottom side of the module components with a maximum height of 1 8mm are permitted Components soldered on the top side of the module can be up to a maximum of 3mm in height Figure 79 Maximum...

Page 78: ...m between carrier board surface and module components when using a module connector with 3mm stacking height To minimize the risk of any mechanical conflict it is recommended not to place components on the carrier board directly under the module that are taller than 1mm Figure 80 Maximum height of carrier board components under module 0 80 1 20 Heatsink Module Components Top Side Module Components...

Page 79: ...ICO 37 38 ETH1_MDI3 PCI Express GND 39 40 ETH1_MDI3 PCIE1_RX 41 42 ETH1_ACT PCIE1_RX 43 44 ETH1_LINK GND 45 46 ETH1_CTREF PCIE1_TX 47 48 ETH1_MDI0 PCIE1_TX 49 50 ETH1_MDI0 GND 51 52 VCC PCIE1_CLK 53 54 ETH1_MDI1 PCIE1_CLK 55 56 ETH1_MDI1 Reserved for type specific features GND 57 58 VCC USB TS_DIFF1 59 60 USBO1_VBUS TS_DIFF1 61 62 USBO1_SSRX TS_1 63 64 USBO1_SSRX TS_DIFF2 65 66 VCC TS_DIFF2 67 68 ...

Page 80: ...IFF16 151 152 MMC1_D5 GND 153 154 MMC1_CLK TS_DIFF17 155 156 MMC1_D6 TS_DIFF17 157 158 MMC1_D7 TS_6 159 160 MMC1_D0 TS_DIFF18 161 162 MMC1_D1 TS_DIFF18 163 164 MMC1_CD GND 165 Parallel Camera CAM1_D7 173 174 VCC_BACKUP SDIO CAM1_D6 175 176 SD1_D2 CAM1_D5 177 178 SD1_D3 CAM1_D4 179 180 SD1_CMD CAM1_D3 181 182 GND CAM1_D2 183 184 SD1_CLK CAM1_D1 185 186 SD1_D0 CAM1_D0 187 188 SD1_D1 GND 189 190 SD1_...

Page 81: ...2 USBO1_OC LCD1_R6 263 264 LVDS1_A_TX2 LCD1_R7 265 266 LVDS1_A_TX2 GND 267 268 GND LCD1_G0 269 270 LVDS1_A_TX3 LCD1_G1 271 272 LVDS1_A_TX3 LCD1_G2 273 274 USBO1_EN LCD1_G3 275 276 LVDS1_B_CLK LCD1_G4 277 278 LVDS1_B_CLK LCD1_G5 279 280 GND LCD1_G6 281 282 LVDS1_B_TX0 LCD1_G7 283 284 LVDS1_B_TX0 GND 285 286 BKL1_ON LCD1_B0 287 288 LVDS1_B_TX1 LCD1_B1 289 290 LVDS1_B_TX1 LCD1_B2 291 292 GND LCD1_B3 ...

Page 82: ...Toradex AG All rights reserved All data is for information purposes only and not guaranteed for legal purposes Information has been carefully checked and is believed to be accurate however no responsibility is assumed for inaccuracies Brand and product names are trademarks or registered trademarks of their respective owners Specifications are subject to change without notice ...

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