
Chapter 6 BIOS Configuration
TI6VG4 User’s Manual
47
CPU to PCI Write Buffer
When enabled, this option increases the efficiency of the PCI bus to and
speed up the execution in the processor. By default, this field is set to
Enabled
.
PCI Dynamic Bursting
When enabled, this option combines several PCI cycles into one. By
default, this field is set to
Enabled
.
PCI Master 0 WS Write
When enabled, this option increases the write cycle speed. By default,
this field is set to
Disabled
.
PCI Delay Transaction
When enabled, this option delays PCI data transaction. By default, this
field is set to
Enabled
.
PCI#2 Access #1 Retry
This item enables PC#2 Access #1 attempts. By default, this field is set to
Disabled
.
AGP Master 1 WS Write
When enabled, writes to the AGP bus are executed with 1 wait states. By
default, this field is set to
Enabled
.
AGP Master 1 WS Read
When enabled, reads to the AGP bus are executed with 1 wait states. By
default, this field is set to
Enabled
.
Assign IRQ for USB/VGA
These fields allow you to enable or disable the IRQ for USB and VGA.
By default, these fields are enabled.
Summary of Contents for TI6VG4
Page 1: ...TI6VG4 Pentium II III Apollo Pro 133 A ATX Motherboard User s Manual Version 1 1 ...
Page 6: ...Chapter 1 Introduction 2 TI6VG4 User s Manual This page was intentionally left blank ...
Page 16: ...Chapter 3 Hardware Description 12 TI6VG4 User s Manual This page was intentionally left blank ...
Page 22: ...Chapter 5 Installation 18 TI6VG4 User s Manual Figure 3 Connector Location on the TI6VG4 ...
Page 26: ...Chapter 5 Installation 22 TI6VG4 User s Manual ...