CHARACTERISTICS
46
NV10B - Manual - 04 - 2022
All undervoltage elements can produce the Breaker Failure output if the
U< BF
and
U<< BF
pa-
rameters are set to
ON.
The parameters are available inside the
Set \ Profile A(or B) \ Undervoltage
- 27 \
U< Element
(
U<< Element) \ Setpoints
menus.
[1]
All the named parameters can be set separately for
Profile A
and
Profile B
(
Set \ Profile A(or B) \
Undervoltage - 27 \
U< Element
(
U<< Element) \ Setpoints
menus).
For every of the two thresholds the logic block can be set.
Logical block (Block1)
If the
U<BLK1
and/or
U<<BLK1
enabling parameters are set to
ON
and a binary input is designed
for logical block (Block1), the protection is blocked off whenever the given input is active.
The trip timer is held in reset condition, so the operate time counting starts when the input block goes
down.
[2]
The enabling parameters are available inside the
Set \ Profile A(or B) \ Undervoltage - 27 \
U< Element
(
U<< Element) \ Setpoints
menus, while the
Block1
function must be assigned to the
selected binary input inside the
Set \ Inputs \ Binary input IN1(x)
menus (IN1 or INx matching)
.
Note 1 The common settings concerning the Breaker failure protection are adjustable inside the
Breaker Failure - BF
menu.
Note 2 The exhaustive treatment of the logical block (Block 1) function may be found in the “Logic Block” paragraph inside
CONTROL AND MONITOR-
ING
section.
all-F27.ai
U
U< Element
U<< Element
Start U<<
Start U<<
Start U<
Trip U<
Trip U<<
&
U< disbyU<<
U< inhibition
t
U< def
t
U< inv
U<
def
t
U<< def
U<<
def
U<
inv
U< Curve
U< Enable
State
Block1
BLK1U<
&
U<BLK1
Start U<
&
Block1
BLK1U<<
&
U<<BLK1
Start U<<
&
U<BF
Trip U<
&
U<BF
U
AND
U
U
L1
,
U
L2
,
U
L3
OR
Common configuration
Logic27
General logic diagram of the undervoltage elements - 27
Fun-F27_S2.ai
Logic diagram concerning the second threshold (U<<) of the undervoltage element - 27
RESET
t
U<<
0
T
TR
IP
PIN
G
M
AT
RIX
(
LE
D+R
EL
AY
S)
t
U<<def
Start U<<
Start U<<
Trip U<<
Trip U<<
Trip U<<
BF Enable (ON
≡
Enable)
towards BF logic
&
U<< BF
&
&
&
Enable (ON
≡
Enable)
Block1 input (ON
≡
Block)
Block1
Block1
&
(ON
≡
Inhibit)
U< Inhibition
U<disbyU<<
Binary input INx (x=1...8-16)
T
0
Logic
INx
t
ON
INx
t
ON
INx
t
OFF
T
0
n.o.
n.c.
INx
t
OFF
U<<ST-K
U<<TR-K
U<<ST-L
U<<TR-L
U<<BF
BLK1U<
U<<BLK1
Logic27
≥1
&
U
L1
U
L2
U
L3
&
State
U
≤
U<
def
U
<<
def
