35
First issue 10 / 04
MAIN BOARD SCHEMATIC DIAGRAM: DIGITAL SYSTEM (HSYN SW & CLOCK GEN.)
DVI-H,V, CLK
1
A/B
Y
0
RGB-H,V,CLK
FGHS
FGVS
DATACK
P[7]
DVI_HS
P[8]
DVI_PICK
P[5]
PIHS
P[5]
PIHSS
P[7]
FGVS
P[7,8,9]
PICLK
P[5]
RGBn_DVI
P[1,10]
DVI_VS
P[8]
PIVS
P[5]
FGHS
P[7,9]
PLLHSO
P[7]
DDCVSYNC
P[7]
D
V33SB
D
D
D
C49
N
U15
74LVC157
2
3
5
6
11
10
14
13
1
15
4
7
9
12
16
8
1A
1B
2A
2B
3A
3B
4A
4B
A/B
G
1Y
2Y
3Y
4Y
VCC
GND
R78
33
1/16W
C50
0.1uF
25V
Z
T
C404
22PF
50V
R77
33
1/16W
R386
150 1/16W
R79
33
1/16W
FROM CPU
POCLK
CLK
POCLKOSD P[2]
PLLCLK
P[1]
PLLDATA
P[1]
CLK
P[5,6]
POCLK
P[4,5]
D
D
D
D
D
VCCPLL
V33
D
D
VCCPLL
D
C57
0.1uF
25V
Z
TP13
T
C53
N/47PF
50V
C56
0.1uF
25V
Z
U16
ICS9161A
13
3
6
7
5
1
2
4
8
9
10
11
12
14
15
16
VDD
AVDD
X1
X2
GND
SEL0_CLK
SEL1_DATA
OE
MCLK
VCLK
ERROUT
EXTCLK
INIT0
INIT1
EXTSEL
PD
T
C52
12PF
50V
R82
4.7
1/16W
R350
N/1M
1/16W
R83
33
1/16W
Y3
14.318MHz
T C51
12PF
50V
T
C54
33PF
50V
L13
0
1/8W
+ C55
47uF
16V
R80
33
1/16W
R81
33
1/16W
