Software Overview
31
SBOU123A – March 2012 – Revised September 2016
Copyright © 2012–2016, Texas Instruments Incorporated
XTR108EVM-USB Evaluation Board and Software Tutorial
5.1.7
SPI Interface
In normal operation, the XTR108 reads data from an external EEPROM to retrieve calibrated register
settings. This operation is accomplished by a read-back controller on the XTR108. The read-back
controller defaults to being active when the XTR108 is powered on and is continuously active unless
disabled. In other words, it starts a new read operation as soon as the previous operation is completed. A
control bit (RBD) in Control Register 2 (register 4) is provided to allow the XTR108 to read the EEPROM
once and then stop.
When calibrating the XTR108EVM-USB, it is required that the automatic EEPROM read-back be disabled,
so that new values written to the XTR108 registers during the calibration procedure are not immediately
overwritten. The calibration functions built into the XTR108EVM-USB software also write new register
values to the EEPROM so that post-calibrated values are automatically loaded at power-up. The SPI
Interface section of the block diagram shows whether the automatic EEPROM read-back is enabled or
disabled.
5.1.8
Alarm Config
The XTR108 Alarm Configuration register (register 7) determines whether the XTR108 goes overscale or
underscale for various detected fault conditions at the PGA input.
defines the behavior of these
settings. If a bit corresponding to the particular error is set to '1', the output goes overscale when the error
occurs. If a bit corresponding to the particular error is set to '0', the output goes underscale when the error
occurs. The Alarm Config section of the block diagram shows the hexadecimal value of the Alarm
Configuration register.
(1)
A high reading indicates that the input exceeds the positive common-mode range; a low reading indicates that the input exceeds
the negative common-mode range; and N indicates that the input is within the common-mode range.
Table 25. Alarm Configuration Register
(1)
BIT
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
V
INN
High
Low
Low
High
N
N
Low
High
V
INP
Low
High
Low
High
Low
High
N
N
