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2.12.3
Remote Interrupts
2.12.4
Serial Bus Error Interrupts
2.13 DMA Event Support
Peripheral Architecture
Remote interrupts occur when an interrupt packet is received over the serial interface from a remote
device. The interrupt status is extracted from the packet and written to a location pointed to by the
interrupt pointer register (INTPTR).
The INTPTR should contain the address of the interrupt pending/set register (INTPENDSET). To get
INTPTR to contain the address of INTPENDSET, program INTPTR with a value of 14h (the offset for
INTPENDSET). Additionally, the INT2CFG bit in the VLYNQ control register (CTRL) must be set to 1,
dictating that the VLYNQ writes to a local register space (in this case, INTPENDSET).
Once an interrupt packet is received over the serial interface, the interrupt status is extracted and written
to INTPENDSET. After the interrupt status is extracted and written to INTPENDSET, the interrupt
generation occurs as previously described in
Section 2.12.2
.
The following summarizes the steps that are required to ensure that the device receives the remote
interrupts:
•
Program the VLYNQ interrupt pointer register (INTRPTR) with a value of 14h, which is the offset
address of the VLYNQ interrupt/pending set register (INTPENDSET).
•
Set the INT2CFG bit to 1 in the VLYNQ control register (CTRL).
Due to erroneous transmit packets that are detected by remote devices (remote error) or errors in the
inbound packets (local error), the serial bus errors result in the setting of the RERROR or LERROR bits in
the VLYNQ status register (STAT).
Additionally, if the INTENABLE bit is set in the VLYNQ control register (CTRL), setting the RERROR or
LERROR bits cause these status interrupts to post to the interrupt pending/set register (INTPENDSET),
causing the VLYNQINT to be asserted to the ARM CPU.
To ensure that serial bus errors result in interrupts to notify the application software, you must perform the
following steps:
1. Set the INTENABLE bit to 1 in the VLYNQ control register (CTRL).
2. Set the INTVEC bits in CTRL to point to a free bit in the VLYNQ interrupt pending/set register
(INTPENDSET). The serial bus error should result in setting the bits in INTPENDSET that are not used
by the application software for other interrupts (bit locations written directly in INTPENDSET or via
remote interrupts).
3. During VLYNQ initialization, the RERROR bit is set after the VLYNQ module achieves a link. When the
link bit is set in the VLYNQ status register (STAT), write a 1 to the RERROR bit. Writing a 1 to the
RERROR bit clears the RERROR bit and prevents the software interrupt handler from seeing the first
RERROR as a legitimate serial bus error interrupt.
The VLYNQ module on the DM644x device is classified as a master peripheral. Classification as a master
peripheral normally implies that the peripheral is able to sustain its own transfers without relying on any
external peripherals (for example, the system DMA, etc). However, the VLYNQ module does not have an
internal DMA (as some other master peripherals).
Therefore, it is likely that the VLYNQ module can rely on the on-chip enhanced DMA (EDMA3) controller
for performing burst transfer. The EDMA3 can still be used to perform burst transfers out to remote
VLYNQ memory map (writes). This use model provides better throughput with less overhead.
Note:
There is no VLYNQ event that allows hardware synchronization to occur with the EDMA3
controller on the DM644x device.
The VLYNQ module uses a 16-word deep FIFO to buffer the burst writes. Since the EDMA3 controller is
much faster compared to the serial VLYNQ interface, a data back-up can occur. Therefore, configuring
EDMA3 for optimal transfer size, etc. is essential.
SPRUE36A – September 2007
VLYNQ Port
23
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