Texas Instruments UCD90240EVM-704, User Manual, Page: 7 / 38

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Test Setup
Table 2. Connector Definition (continued)
Connectors Pins Name Description
J6 1 EN17 Rail enable output
2 EN18 Rail enable output
3 EN19 Rail enable output
4 EN20 Rail enable output
5 EN21 Rail enable output
6 EN22 Rail enable output
7 EN23 Rail enable output
8 EN24 Rail enable output
J7 1 LGPO1 Logic GPO output
2 LGPO2 Logic GPO output
3 LGPO3 Logic GPO output
4 LGPO4 Logic GPO output
5 LGPO5 Logic GPO output
6 LGPO6 Logic GPO output
7 LGPO7 Logic GPO output
8 LGPO8 Logic GPO output
J8 1 LGPO9 Logic GPO output
2 LGPO10 Logic GPO output
3 LGPO11 Logic GPO output
4 LGPO12 Logic GPO output
5 GPIO1 General Purpose I/O
6 GPIO2 General Purpose I/O
7 GPIO3 General Purpose I/O
8 GPIO4 General Purpose I/O
J9 1 PMBUS_ADDR0 PMBus address pin
2 PMBUS_ADDR1 PMBus address pin
3 PMBUS_ADDR2 PMBus address pin
4 SYNC_CLOCK Sync Clock pin
5 GPIO21 General Purpose I/O
6 GPIO22 General Purpose I/O
7 GPIO23 General Purpose I/O
8 GPIO24 General Purpose I/O
J10 1 GPIO13 General Purpose I/O
2 GPIO14 General Purpose I/O
3 GPIO15 General Purpose I/O
4 GPIO16 General Purpose I/O
5 GPIO17 General Purpose I/O
6 GPIO18 General Purpose I/O
7 GPIO19 General Purpose I/O
8 GPIO20 General Purpose I/O
7 SLVUAF3A – March 2015 – Revised March 2015 UCD90240EVM-704 24-Rail Sequencer Development Board
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