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Appendix A Subset of the TVP5154A VDP I

C Registers

VDP Closed Caption Data

Address

90h-93h

Read only

Address

90h

Closed Caption Field 1 byte 1

91h

Closed Caption Field 1 byte 2

92h

Closed Caption Field 2 byte 1

93h

Closed Caption Field 2 byte 2

These registers contain the closed caption data arranged in bytes per field.

VDP WSS/CGMS Data

Address

94h-99h

WSS/CGMS NTSC:
Read only

Address

Byte

94h

WSS/CGMS Field 1 byte 1

95h

b13

b12

b11

b10

WSS/CGMS Field 1 byte 2

96h

b19

b18

b17

b16

b15

b14

WSS/CGMS Field 1 byte 3

97h

WSS/CGMS Field 2 byte 1

98h

b13

b12

b11

b10

WSS/CGMS Field 2 byte 2

99h

b19

b18

b17

b16

b15

b14

WSS/CGMS Field 2 byte 3

These registers contain the wide screen signaling data for NTSC.

Bits 0 - 1

Represent word 0, aspect ratio

Bits 2 - 5

Represent word 1, header code for word 2

Bits 6 - 13

Represent word 2, copy control

Bits 14 - 19

Represent word 3, CRC

WSS/CGMS PAL/SECAM:
Read only

Address

Byte

94h

WSS/CGMS Field 1 byte 1

95h

b13

b12

b11

b10

WSS/CGMS Field 1 byte 2

96h

Reserved

97h

WSS/CGMS Field 2 byte 1

98h

b11

b10

WSS/CGMS Field 2 byte 2

99h

Reserved

These registers contain the wide screen signaling data for PAL/SECAM:

Bits 0 - 3

Represent group 1, aspect ratio

Bits 4 - 7

Represent group 2, enhanced services

Bits 8 - 10

Represent group 3, subtitles

Bits 11 - 13

Represent group 4, others

TVP5154A VBI Quick Start

SLEA104 – July 2010

Summary of Contents for TVP5154A

Page 1: ... 9 VBI Raw Data Mode 10 Appendix A Subset of the TVP5154A VDP I2 C Registers 12 Appendix B Sample WinVCC CMD File for VBI Setup 20 Appendix C Example TVP5154A C Code 21 Appendix D VBI Raw Data I2 C Registers 22 List of Figures 1 The VDP Configuration RAM is Loaded Prior to Line Mode Register Setup 3 2 Example Load of WSS CGMS Configuration RAM 5 3 Line Mode Setup for WSS CGMS 6 4 Example WSS CGMS ...

Page 2: ...2 2 EIA 608 D WSS CGMS PAL 23 field 1 2 14 bits ITU R BT 1119 1 WSS CGMS NTSC 20 field 1 2 20 bits IEC 61880 VITC PAL 6 22 9 SMPTE 12M 1999 VITC NTSC 10 20 9 SMPTE 12M 1999 VPS PDC PAL 16 13 ETS 300 231 V Chip NTSC 21 field 2 2 EIA 744 A Gemstar 1x NTSC 2 Gemstar 2x NTSC 5 with frame byte User Any Programmable Programmable A host or backend receiver can retrieve the sliced data using one of three ...

Page 3: ...www ti com Introduction Figure 1 The VDP Configuration RAM is Loaded Prior to Line Mode Register Setup 3 SLEA104 July 2010 TVP5154A VBI Quick Start Copyright 2010 Texas Instruments Incorporated ...

Page 4: ...0D 0 7 0 10 0 Reserved 0C0h Reserved CC PAL SECAM 0D0h AA 2A FF 3F 04 51 6E 02 A4 7B 09 0 0 0 27 0 Reserved 0E0h Reserved CC NTSC 0F0h AA 2A FF 3F 04 51 6E 02 63 8C 09 0 0 0 27 0 Reserved 100h Reserved WSS CGMS PAL SECAM 110h 5B 55 C5 FF 0 71 6E 42 A4 CD 0F 0 0 0 3A 0 Reserved 120h Reserved WSS CGMS NTSC 130h 38 0 3F 0 0 71 6E 43 63 7C 08 0 0 0 39 0 Reserved 140h Reserved VITC PAL SECAM 150h 0 0 0...

Page 5: ...M starting address a Write 30h to register C4h C RAM address 7 0 b Write 01h to register C5h C RAM address 8 2 Write the two bytes 38h and 00h a Write 38h to register C3h Write first byte to C RAM address 130h b Write 00h to register C3h Write next byte to C RAM address 131h Figure 2 Example Load of WSS CGMS Configuration RAM 3 Line Mode Registers After the VDP Configuration RAM is loaded the Line...

Page 6: ...ded in this example is an I2 C write to the Pixel Alignment Registers CBh CCh which define the horizontal position where data slicing begins The value used 4Eh is recommended for all data services Table 3 Line Mode Configuration Bits for Supported Modes Line Mode Register Name Video Line Number Description D0h FCh Bits 3 0 0000b WST SECAM 6 23 field 1 2 Teletext SECAM 0001b WST PAL B 6 22 field 1 ...

Page 7: ... 97h 99h VDP VPS PAL Gemstar 2x NTSC 9Ah A6h Data VDP VITC Data A7h AFh The internal 512 byte FIFO is used primarily for high bandwidth teletext acquisition but can also be used for capture of the other data services if enable in the Line Mode register A header containing information about the sliced data precedes all sliced data that is routed to the FIFO The FIFO can be directly accessed by the ...

Page 8: ...t 0 of the VDP FIFO output control register CDh must be set to logic 1 to enable host access to the FIFO A header containing information about the sliced data precedes all sliced data that is routed to the FIFO A VDP FIFO Interrupt threshold register C8h FIFO word count register C7h and FIFO full empty status bits C6h are available for managing FIFO data flow 8 TVP5154A VBI Quick Start SLEA104 Jul...

Page 9: ... 0 1 0 DID2 DID1 DID0 Data ID DID 4 NEP EP F5 F4 F3 F2 F1 F0 Secondary data ID SDID 5 NEP EP N5 N4 N3 N2 N1 N0 Number of 32 bit data NN 6 Video line 7 0 Internal Data ID0 IDID0 7 0 0 0 Data error Match 1 Match 2 Video line 9 8 Internal Data ID1 IDID1 8 1 Data Data byte 1st word 9 2 Data Data byte 10 3 Data Data byte 11 4 Data Data byte m 1 Data Data byte Nth word m data Data byte CS 7 0 Checksum 4...

Page 10: ...t VBLK interval for the TVP5154A is defined as lines 1 through 20 for 525 line video formats and lines 623 through 23 for 625 line formats The TVP5154A VBLK interval can be adjusted with the VBLK Start and Stop registers 18h 19h The TVP5154A VBLK Start and Stop registers provide relative adjustments to the default VBLK interval After configuring the desire VBLK interval the Luma bypass bit 4 in th...

Page 11: ...les Present Raw Data Mode disabled Figure 6 Line 21 Closed Caption ITU R BT 656 Digital Output Capture in Raw Data Mode UV chroma data are replaced with Y luma data Note The full scale transitions are embedded sync codes 11 SLEA104 July 2010 TVP5154A VBI Quick Start Copyright 2010 Texas Instruments Incorporated ...

Page 12: ...byte 2 99h b19 b18 b17 b16 b15 b14 WSS CGMS Field 2 byte 3 These registers contain the wide screen signaling data for NTSC Bits 0 1 Represent word 0 aspect ratio Bits 2 5 Represent word 1 header code for word 2 Bits 6 13 Represent word 2 copy control Bits 14 19 Represent word 3 CRC WSS CGMS PAL SECAM Read only Address 7 6 5 4 3 2 1 0 Byte 94h b7 b6 b5 b4 b4 b2 b1 b0 WSS CGMS Field 1 byte 1 95h b13...

Page 13: ... Address 7 6 5 4 3 2 1 0 9Ah EPG Frame Code 9Bh EPG byte 1 9Ch EPG byte 2 9Dh EPG byte 3 9Eh EPG byte 4 9Fh Reserved A0h Reserved A1h Reserved A2h Reserved A3h Reserved A4h Reserved A5h Reserved A6h Reserved VDP VITC Data Address A7h AFh Read only Address 7 6 5 4 3 2 1 0 A7h VITC Frame byte 1 A8h VITC Frame byte 2 A9h VITC Seconds byte 1 AAh VITC Seconds byte 2 ABh VITC Minutes byte 1 ACh VITC Min...

Page 14: ...The configuration RAM data is provided to initialize the VDP with initial constants The configuration RAM is 512 bytes organized as 32 different configurations of 16 bytes each The first 12 configurations are defined for the current VBI standards An additional 2 configurations can be used as a custom programmed mode for unique standards like Gemstar Address C3h is used to read or write to the RAM ...

Page 15: ...the header this goes into the FIFO Even if the full error flag is set FIFO empty 0 FIFO is not empty 1 FIFO is empty TTX available 0 Teletext data is not available 1 Teletext data is available CC field 1 available 0 Closed caption data from field 1 is not available 1 Closed caption data from field 1 is available CC field 2 available 0 Closed caption data from field 2 is not available 1 Closed capt...

Page 16: ...hese registers form a 10 bit horizontal pixel position from the falling edge of sync where the VDP controller initiates the program from one line standard to the next line standard For example the previous line of teletext to the next line of closed caption This value must be set so that the switch occurs after the previous transaction has cleared the delay in the VDP but early enough to allow the...

Page 17: ... register enables the full field mode In this mode all lines outside the vertical blank area and all lines in the line mode register programmed with FFh are sliced with the definition of register FCh Values other than FFh in the line mode registers allow a different slice mode for that particular line 17 SLEA104 July 2010 TVP5154A VBI Quick Start Copyright 2010 Texas Instruments Incorporated ...

Page 18: ...ne 14 Field 2 E2h Line 15 Field 1 E3h Line 15 Field 2 E4h Line 16 Field 1 E5h Line 16 Field 2 E6h Line 17 Field 1 E7h Line 17 Field 2 E8h Line 18 Field 1 E9h Line 18 Field 2 EAh Line 19 Field 1 EBh Line 19 Field 2 ECh Line 20 Field 1 EDh Line 20 Field 2 EEh Line 21 Field 1 EFh Line 21 Field 2 F0h Line 22 Field 1 F1h Line 22 Field 2 F2h Line 23 Field 1 F3h Line 23 Field 2 F4h Line 24 Field 1 F5h Li...

Page 19: ...efault Bits 3 0 0000 WST SECAM 0001 WST PAL B 0010 WST PAL C 0011 WST NTSC 0100 NABTS NTSC 0101 TTX NTSC 0110 CC PAL 0111 CC NTSC 1000 WSS CGMS A PAL 1001 WSS CGMS NTSC 1010 VITC PAL 1011 VITC NTSC 1100 VPS PAL 1101 Gemstar 2x Custom 1 1110 Custom 2 1111 Active video VDP off default A value of FFh in the line mode registers is required for any line to be sliced as part of the full field mode VDP F...

Page 20: ...de registers for a typical PAL VBI setup For PAL systems the Line Mode register has a 3 line offset relative to the actual line number Each command shown writes 1 byte to the I2C address specified in the command line BEGIN_DATASET DATASET_NAME TVP5154A PAL VDP VBI SETUP INCLUDE VDPRegsIdle inc Set VDP registers to their default FFh state INCLUDE SlicerRAM_601 inc Load VDP configuration RAM WR_REG ...

Page 21: ...4E Set Pixel Alignment 7 0 to 0x4E I2CWriteByte TVP5154A 0xCC 0x00 Set Pixel Alignment 9 8 to 0x00 NTSC WSS CGMS Line Mode setup for line 20 of both fields I2CWriteByte TVP5154A 0xEC 0x09 line 20 field 1 0xEC mode bits 0x09 I2CWriteByte TVP5154A 0xED 0x09 line 20 field 2 0xED mode bits 0x09 PAL WSS CGMS Line Mode setup for line 23 source input of both fields PAL line numbering has 3 line offset so...

Page 22: ...ing as defined by registers 18h and 19h This feature may be used to prevent distortion of test and data signals present during the vertical blanking interval Luma signal delay with respect to chroma signal in pixel clock increments range 8 to 7 pixel clocks 1111 8 pixel clocks delay 1011 4 pixel clocks delay 1000 1 pixel clocks delay 0000 0 pixel clocks delay default 0011 3 pixel clocks delay 0111...

Page 23: ...line before stop of vertical blanking interval 1111 1111 128 lines before stop of vertical blanking interval Vertical blanking is adjustable with respect to the standard vertical blanking intervals The setting in this register determines the timing of the GPCL VBLK signal when it is configured to output vertical blank see register 03h The setting in this register also determines the duration of th...

Page 24: ...ch statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications o...

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