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Hardware Configuration
Table 4. FPGA FMC connector (J5) description of the TSW14J10 (continued)
LA17_P/N_CC_A
D20/D21
FPGA-to-FMC
Spare IO signal, 2.5V level
LA23_P/N_A
D23/D24
FPGA-to-FMC
Spare IO signals, 2.5V level
LA16_P_A
G18
FPGA-to-FMC
Spare IO signal, adjustable level*
SP1
K20
FPGA-to-FMC
Spare IO signal, adjustable level*
CLK0_M2C_P/N_A
H4/H5
FPGA-to-FMC
Spare FPGA CLK input connections
CLK1_M2C_P/N_A
G2/G3
FPGA-to-FMC
Spare FPGA CLK input connections
* The level of these signals is controlled by SW5 when JP10 has a shunt installed between pins 1-2. With
the shunt installed between pins 2-3, the external voltage applied to TP40 will determine the level of these
signals.
WARNING
In the external supply mode, make sure the external supply does
not exceed 3.3 VDC to prevent damage occurring to the FPGA.
The ANSI/VITA 57.1 standard assigns voltages to certain pins. These are labeled as 12V, 3P3V, and
VADJ nets on the connector page of the schematic. On the TSW14J50, these pins are connected to test
points allowing user-provided voltages at these pin locations.
3.4.2
SMA Connectors
The TSW14J50 has two SMA connectors, J7 and J8, that can be used as a SYNC outputs. These signals
will be driven by the FPGA. Another SMA, J13, can be used as a trigger input to the FPGA. To
synchronize multiple TSW14J50 boards, the user would connect one of the SYNC outputs from a master
TSW14J50 EVM to the EXT Trigger input SMA of a slave TSW14J50 EVM. This function is currently not
available.
3.4.3
JTAG Connectors
The TSW14J50EVM includes one industry-standard JTAG connector that connects to the JTAG ports of
the FPGA. Jumpers on the TSW14J50EVM allow for the FPGA to be programmed from the JTAG
connector or the USB interface. JTAG connector J2 is used for troubleshooting only. The board default
setup is with the FPGA JTAG pins connected to the USB interface. This allows the FPGA to be
programmed by the HSDC Pro software GUI. Every time the TSW14J50EVM is powered-down, the FPGA
configuration is removed. The user must program the FPGA through the GUI after every time the board is
powered-up.
3.4.4
USB I/O Connection
Control of the TSW14J50EVM is through USB connector J9. This provides the interface between the
HSDC Pro GUI running on a Microsoft
®
Windows
®
operating system and the FPGA. For the computer, the
drivers needed to access the USB port are included on the HSDC Pro GUI installation software that can
be downloaded from the web. The drivers are automatically installed during the installation process. On
the TSW14J50EVM, the USB port is used to identify the type and serial number of the EVM under test,
load the desired FPGA configuration file, capture data from ADC EVMs, and send test pattern data to the
DAC EVMs.
9
SLAU576 – May 2014
TSW14J50 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
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