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Functionality
The GUI loads the FPGA with the appropriate firmware and a specific JESD204B configuration, based on
the ADC device selected in the device drop-down window. Each ADC device that appears in this window
has an initialization file (.ini) associated to it. This .ini file contains JESD information, such as number of
lanes, number of converters, octets per frame, and other parameters. This information is loaded into the
FPGA registers after the capture button is clicked. After the parameters are loaded, synchronization is
established between the data converter and FPGA and valid data is then captured into the on-board
memory. See the High-Speed Data Capture Pro GUI Software User's Guide (
SLWU087
) and section 2.3
in the guide for more information. Several .ini files are available to allow the user to load pre-determined
ADC JESD204B interfaces. For example, if the ADC called "ADS42JB69_LMF_421" is selected, the
FPGA will be configured to capture data from the ADS42JB69EVM with the ADC JESD interface
configured for 4 lanes, 2 converters, and 1 octet per frame.
The TSW14J50 device can capture up to 256M 16-bit samples at a maximum line rate of 6.5 Gbps that
are stored inside the on-board DDR3 memory. To acquire data on a host PC, the FPGA reads the data
from memory and transmits it on a serial protocol interface (SPI). An on-board high-speed USB-to-SPI
converter bridges the FPGA SPI interface to the host PC and GUI.
2.2
DAC EVM Pattern Generator (currently, function is not available)
In pattern generator mode, the TSW14J50EVM generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J50. The FPGA stores the
data received into the on-board DDR3 memory. The data from the memory is then read by the FPGA,
converted to JESD204B serial format, then transmitted to a DAC EVM. The TSW14J50 can generate
patterns up to 256M 16-bit samples at a line rate up to 6.5 Gbps.
The GUI comes with several existing test patterns that can be download immediately. The GUI also has a
pattern generation tool that allows the user to generate a custom pattern, then download it to the on-board
memory. See the High-Speed Data Capture Pro Software User's Guide (
SLWU087
) for information. Like
the ADC capture mode, the DAC pattern generator mode uses .ini files to load predetermined JESD204B
interface information to the FPGA.
3
Hardware Configuration
This section describes the various portions of the TSW14J50EVM hardware.
3.1
Power Connections
The TSW14J50EVM hardware is designed to operate from a single supply voltage of +5 V DC. Connect
the +5 V DC output of the provided AC-to-DC power supply to J11 of the EVM. Connect the other power
supply cable to 100-240 VAC, 50 to 60-Hz source. The board can also be powered up by pro5 V
DC to the red test point, TP34, and the return to any black GND test point. The TSW14J50 draws
approximately 0.2 A at power-up and 0.8 A when capturing 4 lanes of data from an ADS42JB69EVM at a
line rate of 2.5 Gpbs.
5
SLAU576 – May 2014
TSW14J50 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
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