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Analog Front End IC TMS37122 - Reference Guide

August ’01

Figure 25: Timing Diagram for Test Mode PTx07

2.11

Resonant Circuit Trimming

The three Resonant Circuits (LR,CR) connected between VCL and the inputs RF1, RF2 and
RF3 need to be trimmed to the optimal system frequency (fTX) in case the tolerances of the
inductance and the external capacitor are too high. Especially for the Battery Backup and
Charge Function an accurate trimming is important because of the energy transfer to the
charge capacitor CL is better.

Each RF-input has a certain input capacitance CIN with respect to GND, which must be taken
into consideration during definition of the resonant circuit components. This capacitor de-
creases with increasing VCL (CRF1, CRF2, CRF3).

As well as this, an 8-bit capacitor array is provided at each RF-input. The Trimming Capac-
itors are activated or deactivated by means of 8-bit EEPROM cells. Per default all capacitors
are programmed off. The external components are selected in a way that the resonant circuit
frequency range resulting from the parameter variations without Trimming Capacitors (but
with Input Capacitance) is below the desired frequency. By switching (programming) on the
binary weighted capacitors the resonant circuit range can be shifted up to achieve symmetri-
cal distribution around the system frequency.

In case the LF Transmission function is used, also the non-configurable Modulation Capaci-
tor (CM) must be taken into consideration when the resonant circuit components are defined.
The resulting frequency hub is depending on the used components and must be adapted to the
Base Station Requirements.

The system manufacturer has to trim the Identification Device after assembly using the Trim/
Test Interface. The following Test Modes are provided:

- PTx14 Programming of Antenna 1 trim byte (on and off)

- PTx24 Programming of Antenna 2 trim byte (on and off)

- PTx34 Programming of Antenna 3 trim byte (on and off)

1

1

2 3 4 5

LSB

VBAT

TDAT

TCLK

TEN

2 3

ROW

NIBBLE

1 2

LSB

LSB

VBAT

WDEEN

TEST MODE

PTx07

6

4

3 1

9

DATA OUT

1 2 3 4

undefined

3DTMOD7.DRW

1

5

BIT 1

BIT 2-4

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Summary of Contents for TRIS TMS37122

Page 1: ...1 August 01 Chapter 3 Application TIRIS Automotive Devices Analog Front End IC TMS37122 Reference Guide 11 09 21 046 August 2001 ...

Page 2: ...I assumes no liability and is not responsible for infringement of patents and or any other intellectual or industrial property rights of third parties which may result from assistance provided by TI TI products are not designed intended authorized or warranted to be suitable for life support applications or any other life critical applications which could involve potential risk of death personal i...

Page 3: ...h and South America the Far East and Aus tralia to provide direct support For more information please contact your nearest TIRIS Sales and Application Center The contact addresses can be found on our home page http www ti rfid com WARNING A WARNING IS USED WHERE CARE MUST BE TAKEN OR A CERTAIN PROCEDURE MUST BE FOLLOWED IN ORDER TO PREVENT INJURY OR HARM TO YOUR HEALTH CAUTION This indicates infor...

Page 4: ... 59 4 2 Recommended System Operating Conditions 60 List of Figures Page Figure 1 TSSOP Package Top View 7 Figure 2 System Arrangement of 3D Analog Front End IC TMS37122 8 Figure 3 Typical 3D AFE Application Including Battery Backup Function 10 Figure 4 Block Schematic of TMS37122 16 Figure 5 Standard Battery Supply Schematic 17 Figure 6 Schematic for Rechargeable Battery Supply 18 Figure 7 Schemat...

Page 5: ...assive Entry Wake Pattern Detection 50 Figure 29 Passive Entry Challenge Response Timing 51 Figure 30 Passive Start Wake Pattern Detection 53 Figure 31 Timing Diagram for Battery Backup Function 55 Figure 32 Timing Diagram of Anti Collision Function 57 Figure 33 Measurement System Timing Dynamic Current Sensitivity 67 List of Tables Page Table 1 Description of the Device s Pins 11 Table 2Default F...

Page 6: ...Description This chapter introduces the TIRIS 3D Analog Front End AFE low voltage low current in terface circuit for microcomputer controlled Automotive Keyless Entry Systems Topic Page 1 1 General Features 7 1 2 References 7 1 3 Circuit Description 8 ...

Page 7: ...oor outdoor detection On Chip Antenna Trimming using EEPROM controlled capacitor arrays On chip digital Channel Sensitivity Adjustment Provides a battery less backup mode using TIRIS compatible FSK transmission Designed for Automotive Requirements 16 pin TSSOP Package Figure 1 TSSOP Package Top View 1 2 References 1 Digital Signature Wedge Transponder RI TRP B9WK Reference Manual 11 09 21 029 July...

Page 8: ... hardware and software capability The achievable distance between transmitter and transponder and the possible data speed de pends on the size and quality factor of the antennas Typical achievable distances are in the range of 1 5 to 2 5 m Figure 2 System Arrangement of 3D Analog Front End IC TMS37122 The 3D AFE can be equipped with up to three antennas covering the three space axes to avoid reduc...

Page 9: ...ennas can reach a very high level due to induced voltage To avoid damage of the integrated circuit the inputs RF and VCL are protected by Voltage Limiter circuits The transmission back to the base station is using the TIRIS HDX FSK modulation and the telegrams can therefore be made compatible to current battery less TIRIS transponder sys tems For this purpose a simple two wire interface to the Mic...

Page 10: ...e internal pull down resistors in order to save current Therefore defined states from the connected Microcomputer are required If pins are not used a connection to GND is necessary CL VCL GND WAKE VBAT EOBA GND UHF TRANSMITTER WDEEN VCCO VCC RF1 RF2 RF3 TIMER INT INP INT INP OUT TEST TRIMMING INTERFACE TCLK TDAT OUT BATTERY LR1 CR1 TEN 3 D ANALOG FRONT END TMS37122 MICROCOMPUTER OUT MOD LR2 LR3 CR...

Page 11: ...ssive Entry circuitry A battery with 3 0 V nominal supply voltage must be connected here A capacitor equal to or greater than 22 nF should be connected between VBAT and GND to buffer the VBAT supply 7 EOBA Out Output of the End of Burst Detector The Microcomputer receives amplitude modulated commands and data from the Base Station via this pin The Microcomputer might use the EOBA signal together w...

Page 12: ...t and configuration interface The data is shifted in and out with the rising edge of TCLK 14 RF2 In Device connection pin for the antenna resonator 2 The antenna resonator consists of a low Q parallel LC circuit The other end of the resonator is connected to pin VCL 15 RF1 In Connection pin for the antenna resonator 1 The antenna resonator consists of a low Q parallel LC circuit The other end of t...

Page 13: ... 17 2 2 1 2 Rechargeable Battery Supply 17 2 2 1 3 Battery Backup Supply 18 2 2 2 VCL Supply 19 2 2 2 1 Backup Mode 19 2 2 2 2 Test Mode 20 2 3 Power on reset 22 2 4 Limiter Circuits 23 2 5 Wake Detector 24 2 6 End of burst Detector 25 2 7 Pulse Position Demodulator 25 2 8 Control Unit 26 2 8 1 Off Mode 28 2 8 2 Standby Mode 28 2 8 3 Init Mode 28 2 8 4 Active Mode 28 2 8 4 1 Wake Pattern Detection...

Page 14: ...r Threshold 38 2 10 3 4 Wake Pattern Detection Flag NO_WAKE 39 2 10 3 5 Write Distance Expander 2 Flag NO_WDE2 39 2 10 3 6 Write Distance Expander 3 Flag NO_WDE3 39 2 10 3 8 Passive Entry Wake Pattern 40 2 10 3 9 Passive Start Wake Pattern 40 2 10 3 10Telegram Duration C_TELEGR 40 2 10 3 11Wake Pattern Waiting Time C_WAIT 41 2 10 4 Memory Programming 42 2 10 5 Memory Read 43 2 11 Resonant Circuit ...

Page 15: ...rent protection diode Clock Regenerator for Pluck Circuit and modulation clock divider Divider for modulation clock CLKM Continuous Pluck Circuit Antenna 1 only Pluck Synchronization for modulation function Antenna 1 only Modulation Capacitor CM Antenna 1 only Wake Detectors 3 fold EOBA Detector 3 fold Signal Selector Pulse Position Demodulator for Wake Pattern only Wake Pattern Comparator Watchdo...

Page 16: ...TOR 3 VBAT CONTROL UNIT WITH CONFIGURATION EEPROM SIGNAL SELECTOR WDEEN TEST PTx34 EOBA DETECTOR WAKE PATTERN COMPARATOR PULSE POSITION DEMODULATOR EOBA EEPROM WAKE1 EEPROM WAKE2 CLKA M CT8 CT1 TEST PTx28 SINGLE PLUCK TX TCLK TDAT TEN Referenced to VBAT WAKE CLKM VWAKE A2 3 VBAT VCL VBAT RECTIFIER RECTIFIER 8 Bit TRIMMING EEPROM VWAKE B2 3 WAKE DETECTOR 2 VBAT VWAKE A2 3 VWAKE B2 3 WAKE DETECTOR 1...

Page 17: ...e Expander function Beside this it is possible to provide an additional LF Channel in order to overcome interference prob lems in this frequency band The LF Response must take place before the UHF transmission and is only possible if the battery voltage is above the minimum specified value because the supply of Microcomputer and 3D AFE is not backed up Figure 5 Standard Battery Supply Schematic 2 ...

Page 18: ...on Device tries to get into the car in Keyless Entry Mode by pulling the door handle he will be not successful if he is too far away from the Base Station Antenna This because the Body Controller will not get a response on his challenge because the 3D AFE and Microcomputer is off After several trials the Body Controller can increase the Wake up Time in order to charge up the charge capacitor to a ...

Page 19: ... of strong activation fields and extended Wake Times For calculation of the capacitor value the following information must be available Supply current of TMS37122 in Transmit Mode Itx This current depends on the quality factor of the resonant circuit At minimum quality factor necessary for Backup Mode Q 10 the current consumption Itx is the sum of IVCL 110µA and Iact 30µA Supply current of the Mic...

Page 20: ...t circuit IVCL At a quality factor of 10 at least a capacitor of 680nF will be required 2 2 2 2 Test Mode The resonant circuit of the Identification Device must be trimmed to optimum resonance after assembly Beside this the desired option bits must be configured in the 3D AFE memory For this purpose a Test Interface is provided connected typically to Tester Unit For engineering purpose also a spec...

Page 21: ...VPP Apply programming voltage for EEPROM TEN must already be at VBAT before programming voltage is applied TCLK 0V Prepare data at TDAT TCLK VBAT Shift TDAT condition at positive transition TDAT 0 Low data Change at negative transition of TCLK TDAT VBAT High data externally supplied Change at negative transition of TCLK TDAT X TDAT is digital output in certain test modes CL VCL GND WAKE VBAT EOBA ...

Page 22: ...m is already equipped with an efficient reset circuit securing an initialization in case of supply voltage drop below 2 V 2 2 V If the Battery Backup function is used we recommend to use a Low Power Supervisory cir cuit Isupply 1 µA One device that could be used is TPS3836 37 Texas Instruments Figure 9 Schematic of Reset Flow RESET RST MICROCOMPUTER VCC VDD TPS3836K25 GND VSS CT OUT WDEEN TMS37122...

Page 23: ... voltage The common VCL pin has an additional VCL Limiter circuit In case of strong fields the RF signal can become very unsymmetrical and therefore the VCL could increase stronger than the RF amplitude In this case the VCL Limiter prevents the low voltage parts from being overstressed The Voltage Regular characteristic also achieves a limitation of the VCCO voltage Under all VCL conditions the VC...

Page 24: ...r is enabled At Wake Detector 1 the level can be configured by the Configuration Memory Level Adjust Detect Wake Detector 2 and 3 have maximum sensitivity The clocks provided by the Clock Regenerator are counted and supervised by the Clock Su pervision circuit which activates at a certain state the EOB Detector An analog watchdog detects missing clocks If at least 2 to 4 clocks are missed the coun...

Page 25: ...is deactivated and increases faster when activated In the far distance range the amplitude drops faster but increases slower After detection of a Wake signal the End Of Burst EOB Detector is activated see Figure 4 The EOB Detector has to detect any LF amplitude drop which exceeds 50 of the initial amplitude and has to convert it into a digital signal EOBI This signal is fed to a Pulse Po sition De...

Page 26: ...ase the negative transition occurs before the threshold is reached and a low bit is shifted Bit by bit the received pattern is compared with the two Wake Pattern Passive Entry Pas sive Start loaded from Configuration Memory during Standby Mode and result is reported to the Control Unit 2 8 Control Unit The Control Unit of the TMS37122 is supplied by the battery voltage VBAT and controls the comple...

Page 27: ...for max tWRX Check Wake Pattern Iact EOBI OFF Wait for tTELEGR Iinit VRF VWAKEA WDEEN LOW WDEEN LOW TX LOW and WDEEN HIGH WAKE PATTERN B received Passive Start WAKE PATTERN A received Passive Entry VWAKEB ON 3DSTAT1G CH4 Transparent M Watchd OFF WAKE High EOBA ON CLKA ON Iact CLKI missed for twdg tTELEGR exceeded CLKI missed for twdg CLKI OFF TX HIGH and WDEEN HIGH WAIT TX LOW TX HIGH TX LOW and W...

Page 28: ... Mode and consumes the Standby Current Istby In this state the unit remains as long as the RF amplitudes of all activated resonant circuits are below the threshold level VWAKEA 2 8 3 Init Mode If a carrier is present and the amplitude at one of the three antennas exceeds the WAKE Sen sitivity Level A WAKESensA1 2 3 for about 1 ms the EOBI detector is activated As soon as the RF Amplitude of one re...

Page 29: ...ted EOBI signal the circuit enters the Wake Pattern receive loop The com plete Wake Pattern must be received in a predetermined time twrx to be accepted This time is not configurable If no valid or complete Wake Pattern is detected during twrx a waiting loop is entered In this loop the circuit remains for an expected time a foreign Identification Device needs to com plete its telegram transmission...

Page 30: ...OBA The watchdog for CLKI is disabled which means that the external Microcomputer has to take over the supervision and Off Mode Iquiet VRF VWAKEA for tWdly No_Wake Flag 0 No modulation during tWAIT CLKI ON EOBI ON DEMOD ON Wait max for tWAIT Iact 1st EOBI detected No valid or complete WAKE PATTERN during tWRX Standby Mode VWAKEA ON Istby Receive Wake Pattern for max tWRX Check Wake Pattern Iact EO...

Page 31: ...e Microcomputer LF Transmission Mode This is the case in the Backup Mode Battery Backup Mode Instead of transmitting the response via UHF Channel the Microcomputer activates the TX input of the TMS37122 after reaching the Transparent Mode see Figure 18 This causes the Continuous Pluck Circuit of the device to activate the oscillation at Resonant Circuit 1 The resulting clock from the VCL supplied ...

Page 32: ...Mode 2 10 Configuration Memory 2 10 1 Memory Organisation The TMS37122 EEPROM Configuration Memory is organized by 3 rows and 5 nibbles Each nibble has 4 bits see Figure 19 The Configuration Memory can be programmed and read via Test Trimming Interface Programming and reading must be done nibble by nibble using test mode PTx04 and PTx07 OFF Iquiet WDEEN LOW WDEEN HIGH WDEEN LOW 3DSTAT5 CH4 Wdg OFF...

Page 33: ...kHz NO_WAKE0 1 Wake Pattern Detection is deactivated NO_WDE2 0 Wake Detector 2 is activated NO_WDE3 0 Wake Detector 3 is activated NO_CLKA 0 CLKA output is activated PE WAKE PATTERN 0000 Passive Entry Wake Pattern is 0 PS WAKE PATTERN 0000 Passive Start Wake Pattern is 0 C_TELEGR 0 cTelegr 0 tTelegr 30 5 ms C_WAIT 0 cwait 0 twait 7 6 ms 0 1 2 3 NIBBLE ROW 1 2 Bit 0 Bit 3 Bit 3 Bit 0 VWAKE B 1 VWAK...

Page 34: ... CLKA is available continu ously or interrupted only shortly during toff If this cannot be achieved due to lower quality factors and thereore stronger damping or if higher data rates are demanded PPM Threshold must be adapted 0 1 2 3 NIBBLE ROW 1 2 Bit 0 Bit 3 Bit 3 Bit 0 VWAKE B 1 VWAKE A 1 Bit 3 Bit 0 VWAKE B 2 3 PPM THRESHOLD Bit 0 Bit 3 Bit 0 4 0 NO WAKE PASSIVE ENTRY WAKE PATTERN C_TELEGR PAS...

Page 35: ...he sensitivity of the air coil an tenna to the sensitivity to the equal ferrite antennas the sensitivity RF1 can be reduced see Table 3 and Figure 21 Table 3 Wake Sensitivity VWAKEA 1 Options Wake Sensitivity DEC VWAKEA 1 min mVpp VWAKEA 1 nom mVpp VWAKEA 1max mVpp MSB LSB 15 2 5 10 1 1 1 1 14 2 5 7 13 2 1 1 1 0 13 3 0 9 0 16 4 1 1 0 1 12 3 5 11 19 6 1 1 0 0 11 4 0 13 0 22 8 1 0 1 1 10 4 5 15 0 26...

Page 36: ... if this lower threshold is exceeded the 3D AFE enters the Transparent Mode and the engine can be started because the Microcomputer can return the correct response The sensitivity level for Passive Start can be adjusted depending on the system behavior The field strength generated outside the car by an internal Passive Start Base Station for example in dashboard must be unable under all circumstan...

Page 37: ...0 27 0 45 0 1 1 0 1 12 20 0 38 0 62 5 1 1 0 0 11 26 0 49 0 80 0 1 0 1 1 10 32 0 60 0 97 5 1 0 1 0 9 38 0 71 0 115 0 1 0 0 1 8 44 0 82 0 132 5 1 0 0 0 7 50 0 93 0 150 0 0 1 1 1 6 56 0 104 0 167 5 0 1 1 0 5 62 0 115 0 185 0 0 1 0 1 4 68 0 126 0 208 0 0 1 0 0 3 74 0 137 0 220 0 0 0 1 1 2 80 0 148 0 237 5 0 0 1 0 1 86 0 159 0 255 0 0 0 0 1 0 92 0 170 0 272 5 0 0 0 0 PE Wake Pattern PS Wake Pattern 3DP...

Page 38: ...on Demodulation Threshold Count cHdet for decoding the PPM Wake Pattern The resulting Threshold Time tHdet depends on the used system frequency tHdet cHdet fTXThe numbers in below table are given for the nominal TIRIS System Frequency fTX 134 2 kHz the default cHdet is 56 0 50 100 150 200 250 300 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CONFIGURATION SENSITIVITY mVpp SPECmin SPECnom SPECmax ...

Page 39: ...ernally Standby current consumption is reduced due to this 2 10 3 7 CLKA Output Disable Flag NO_CLKA If the NO_CLKA flag is set the CLKA M output does not provide a clock when WAKE is activated This prevents back coupling of interference to the sensitive RF inputs due to not optimized PCB layout The option can be used at identification devices which do not require the CLKA This is the case if the ...

Page 40: ...specially if the Base Station uses same modulation principle for data transfer to the transponder 2 10 3 10Telegram Duration C_TELEGR If the Wake Pattern check detected a non valid or incomplete Wake Pattern it can be assumed that a foreign Base Station had requested communication from a foreign Identification De vice To avoid ongoing wake up of the non addressed Identification Device a waiting pe...

Page 41: ...cceptable by the system user and the mini mum communication time is 50 ms the maximum Wake up Time will be around 150 ms Be cause of the exponential rise behavior the charge voltage VCL will reach 63 of the maximum voltage 3 V after 30 ms At this time enough voltage is available at VCCO to initialize the Microcomputer 2 5 V Because the initialization will need some time WDEEN will not be set befor...

Page 42: ...Nibble information is shifted Row and Nibble address is binary coded After that 16 clocks must be supplied while TEN is high in order to clock the internal Control Unit Then the level at TEN can be increased to VPP level and programming is exe cuted Rise and fall time of VPP must be observed With deactivation of TEN the circuit resets automatically and is ready for next test command VBAT and or WD...

Page 43: ...ter nine TCLK pulses the first data bit is already available at output TDAT Then additional five clocks are required for the Control Unit With the negative transition of the next TCLK the Tester Unit must store the first data bit The next three data bits are shifted with the positive transition of TCLK and should be stored by the Tester Unit at the negative transitions Low at TEN resets the test c...

Page 44: ...f The external components are selected in a way that the resonant circuit frequency range resulting from the parameter variations without Trimming Capacitors but with Input Capacitance is below the desired frequency By switching programming on the binary weighted capacitors the resonant circuit range can be shifted up to achieve symmetri cal distribution around the system frequency In case the LF ...

Page 45: ...als should be short tpluck because during this time th RF pin is short circuit to ground and a high current will flow from VCL via the coil This trigger action is further called pluck because the action can be compared with the plucking of a spring which is fasten at one side VCL and pulled down to ground The oscillation fades away depending on the resonant circuit quality factor Because the TMS37...

Page 46: ...ront End IC TMS37122 Reference Guide August 01 Figure 26Timing Diagram for Test Mode PTx18 2 3 4 5 LSB VBAT TDAT TCLK TEN VBAT WDEEN 6 TEST MODE PTx18 VCL PERIOD DURATION MEASUREMENT 10 PULSES 1 1 3DTMD18B DRW RFx ...

Page 47: ...ogramming starts when TEN is ramped up to VPP level The test mode is left with TEN low Result of programming process should be checked by an additional Resonance Frequency Measurement and Trimming EEPROM Programming should be repeated if necessary Figure 27 Timing Diagram for Test Mode PTx14 2 11 3 Modulation Frequency Check During LF Transmission Mode a Frequency Shift Keying signal is transmitte...

Page 48: ... This chapter describes the various functions of the integrated circuit and how they can be used in actual applications Topic Page 3 1 Passive Entry Function 49 3 2 Passive Start Function 52 3 3 Battery Backup Function 54 3 4 Immobilizer Function 56 3 5 Anti Collision Function 56 ...

Page 49: ...rst WAKEI signal determines the receive channel During the Waiting Time the Base Station will start modulation while sending the Passive En try Wake Pattern The internal clock CLKI will be active during this period If the received PE Wake Pattern is equal to the PE Wake Pattern in the EEPROM the RF level check with VWAKEB will NOT be performed and the 3D AFE will activate the output WAKE at once T...

Page 50: ...en this has hap pened the UHF Transmitter is activated and the Response Telegram is sent to the Base Sta tion There the Response is checked and the door is opened if valid The Microcomputer initializes the 3D AFE after transmission of the Response with a short negative pulse at WDEEN The circuit returns to Standby Mode and is ready for next cycle EOBI CLKI 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1...

Page 51: ...ication Figure 29 Passive Entry Challenge Response Timing BASE STATION TXCT 0 1 0 0 WAKE WAKE PATTERN WAKE ID DEVICE WDEEN 0 1 0 0 WAKEI ENCR INIT MC TX MOD CLKA M VCL EOBA UHF TX 3DTIM02A CH4 PE COMMAND CHALLENGE RESPONSE off on ...

Page 52: ...ormed sensitivity stays at VWAKEA level If the level is higher than VWAKEB the output WAKE is set This will cause the Microcomputer of the Identification Device to wake up after an eventually µC Wake Delay Depending on the re quired time the Base Station should insert an active period between Wake Pattern and Com mand transmission The digitized amplitude modulation is output at the EOBA and demodu...

Page 53: ...KI 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 DATA DATI WAKE EOBA µC WAKE DELAY CLKA M PS PATTERN PE PATTERN WAKEI WAKE UP TIME COMMAND CHALLENGE BASE STATION TXCT VWAKEA COMMAND CHALLENGE DATA 3DBTIM01 DRW PASSIVE START WAKE PATTERN VWAKEB tWAIT ID DEVICE WDEEN on off ...

Page 54: ...r because he was advised to do by the car s user manual As a result the charge capacitor in the Identification Device is charged up to a higher voltage see Figure 31 Via the voltage regulator in the 3D AFE the supply voltage of Microcomputer and Front End is increased The Supervisory Circuit will detect sufficient voltage and will restart the Microcomputer After initialization the Microcomputer wi...

Page 55: ... Figure 31 Timing Diagram for Battery Backup Function 0 1 0 0 WAKE WAKE PATTERN WAKE 0 1 0 0 ENCR INIT MC TX MOD CLKA M ID DEVICE VCL EOBA UHF TX 3DTIM03A DRW PE PS BACKUP COMMAND CHALLENGE RF1 WDEEN VBAT RESET BASE STATION TXCT off on ...

Page 56: ...t function the simultaneous UHF Responses initiated by a Challenge might interfere each oth er A solution to this problem is described in a TIRIS Patent 2 which is allowed to use in conjunction with the TMS37122 The Identification Device Microcomputer must have stored for this purpose in its memory a Key Number and eventually a Car Number The Wake Pattern also fulfils the task of a Car Number Let ...

Page 57: ...gure 32 Timing Diagram of Anti Collision Function BASE STATION TXCT 0 1 0 0 WAKE WAKE PATTERN WAKE ID DEVICE WDEEN 0 1 0 0 ENCR INIT MC TX MOD CLKA M VCL EOBA UHF TX COMMAND CAR NUMBER CHALLENGE 3DTIM06A CH4 REQUEST RESPONSE 2 3 4 1 off on ...

Page 58: ...apacitor 61 4 2 3 3 Charge Capacitor 61 4 2 3 4 IC 62 4 2 4 IC Characteristics over Operating Free air Temperature Range 63 4 2 4 1 General IC Characteristics 63 4 2 4 2 Input Capacitances 63 4 2 4 3 Modulation Capacitor 63 4 2 4 4 Trimming Capacitors and Switches 64 4 2 4 5 CLKA Watchdog Circuit 64 4 2 4 6 Clock Regenerator Pluck Logic 65 4 2 4 7 RF Limiter 65 4 2 4 8 VCL Limiter 65 4 2 4 9 Volta...

Page 59: ...Max Unit Operating free air temperature TaR 40 85 ºC Storage Temperature Ts 40 100 ºC Battery Voltage VBAT 0 3 5 5 V Input Voltage VIN MOD TX 0 3 1 1 x VBAT V Input Voltage VIN TEN TCLK TDAT 0 3 1 1 x VBAT V High Level Output Current IOH WAKE CLKA M EOBA TDAT 100 µA Low Level Output Current IOL WAKE CLKA M EOBA TDAT 100 µA Input Current Iant RF1 RF2 RF3 See Note 1 10 mA Note 1 Continuous activatio...

Page 60: ...e to be established in the application Parameter Sign Note Min Nom Max Unit Resonance Frequency fRES ANT1 ANT2 ANT3 VCL 5 V 120 134 2 140 kHz Identification Device Quality Factor QopTRP ANT 1 used for backup function Notes 1 2 10 30 Identification Device Quality Factor QopTRP ANT 1 2 3 no backup function Notes 1 2 20 Low Bit Transmit Frequency fL ANT1 40 85 ºC Qop 10 30 Notes 1 2 130 2 134 7 139 5...

Page 61: ...onant Circuit Capacitor CR fRES 134 2kHz 446 5 470 493 5 pF Dielectric NP0 Temperature Coefficient of CR NP0 dCR CR dT 30 73 ppm K Dielectric R2H Temperature Coefficient of CR R2H dCR CRdT 220 60 ppm K Quality factor QCR 1000 Operating Voltage RF 20 50 Vpp Parameter Sign Note Min Nom Max Unit Charge capacitor CL Backup Function not used 10 22 33 nF Dielectric of CL CLdiel X7R Charge Capacitor Temp...

Page 62: ...tput Current IVCCO VCCO 1 mA Supply Voltage for Trim Test VCL with respect to DG 25 ºC 2 5 VCL VBAT 4 6 V High level input voltage TDAT TCLK TEN VIH VBAT 2 4V 0 95 x VBAT 1 05 x VBAT V Low level input voltage TDAT TCLK TEN VIL VBAT 2 4V 0 0 05 x VBAT V Clock frequency fTC TCLK 100 134 2 1000 kHz Rise and fall time TDAT TCLK TEN tf 500 ns Programming Voltage Vpp TEN pin 15 16 17 V VPP Rise Time trV...

Page 63: ...pF Effective Input Capacitance CRFx CIx dCI dV CRF2 CRF3 VCL 5 V 25 ºC CT off 12 16 20 pF Input Capacitance CI2 CI3 VCL 0 5 V 25 ºC CT off 19 pF Temperature Coefficient of CI1 C2 dCI dT 0 1 pF K Input Capacitance Change CT off dCI dV VCL 3 5V 25 ºC 0 4 0 5 pF V Input Capacitance Change CT on dCI dV VCL 3 5V 25 ºC 0 05 0 1 pF V Input Capacitance Change CT off dCI dV VCL 3 5V 25 ºC 1 1 pF V Input Ca...

Page 64: ...F Trimming Capacitor 7 CT7 25 ºC 32 37 6 43 2 pF Trimming Capacitor 8 CT8 25 ºC 64 75 3 86 6 pF Max Trimming Capacitor CT CT1 CT2 CT8 CT 25 ºC 127 5 15 150 0 172 5 15 pF Voltage Coefficient of CT dCT dV 0 1 pF V Temp Coefficient of CT dCT dT 0 02 pF K On Res Trim Switch 1 RT1 VPP 16 V 800 Ω On Res Trim Switch 2 RT2 VPP 16 V 400 Ω On Res Trim Switch 3 RT3 VPP 16 V 400 Ω On Res Trim Switch 4 RT4 VPP...

Page 65: ...iter Voltage VRFlim Ilim 10 mA 13 17 V RF Limiter Current IRFlim continuous 10 mA Note 1 Continuous activation of one RF input at a time Parameter Sign Note Min Nom Max Unit VCL Limiter Voltage VCLlim Ilim 10 µA 6 V VCL Limiter Voltage VCLlim Ilim 10 mA 7 V VCL Limiter Voltage VCLlim applicative 6 8 V VCL Limiter Current ICLlim continuous 10 mA Parameter Sign Note Min Nom Max Unit VCCO Output Volt...

Page 66: ...cification using a Modulation Generator The currents are measured via a measurement resistor using a Differential Probe The different states of the 3D AFE are reached by push button activation at WDEEN Parameter Sign Note Min Nom Max Unit Quiescent Current Iquiet VBAT 4 V WDEEN 0 V 100 nA Stand by current 3 Antennas Istby VBAT 4 V WDEEN 4V 5 7 µA Stand by current 2 Antennas Istby VBAT 4 V WDEEN 4V...

Page 67: ...EN WAKE EOBA VBAT TMS 37122 3D ANALOG FRONTEND IC TCLK TEN CL 22nF C1 100nF 3DMEA07 ch4 50 Ohm R3 SIGNAL GENERATOR f_RES V_wakeA B C POWER SUPPLY For simulation change of battery 50Ohm f_mod 100 MODULATION GENERATOR 2V 4V MOD TX WDEEN MOD TX VCL VBAT _ Test Trimming Interface V f mod TDAT CLKA M R meas _ I_quiet I_stby I_init I_act R meas 10kOhm 100mV I 10uA DIFF PROBE HP1141A PROBE CONTROL POWER ...

Page 68: ...ivity A Step Size Ant 1 VstepA 1 0 5 2 3 2 mVpp Parameter Sign Note Min Nom Max Unit Wake Sensitivity A Antenna 2 and 3 VwakeA 2 3 Fix 2 5 10 mVpp Parameter Sign Note Min Nom Max Unit Wake Sensitivity B Range Antenna 1 VwakeB 1 Configurable typical range 25 ºC VBAT 3V 5 170 mVpp Wake Sensitivity B Antenna 1 VwakeB 1 Configured to highest sensivity 2 5 10 mVpp Wake Sensitivity B Resolution Antenna ...

Page 69: ...ust 01 Chapter 4 Product Specification Data Wake Sensitivity B Resolution Ant 2 and 3 RESB 2 3 4 Bit Wake Sensitivity B Step Size Ant 2 and 3 VstepB 2 3 6 0 11 0 17 5 mVpp Parameter Sign Note Min Nom Max Unit ...

Page 70: ...a 50 Modulation Depth for idle EOBA m idle Vmax VwakeA Note 1 2 a 96 EOBA Activation Delay dtEOBA VRF VWAKE to VWAKE 2 VBAT 2V 15 46 90 µs EOB Deactivation Delay dtNEOB Step VRF VWAKE 2 to VWAKE VBAT 2V 15 42 60 µs Parameter Sign Note Min Nom Max Unit Coupling Capacity Ccpl 1 pF Input Impedance Low Amplitude Rin Vrf 5mVpp fTX 134 2kHz 2 MΩ Input Impedance High Amplitude Rin Vrf 15Vpp fTX 134 2 kHz...

Page 71: ... DG 25 ºC 7 10 25 kΩ Pull down Resistor TDAT RTDAT with respect to DG 25 ºC VBAT 3 V 70 150 250 kΩ Low Level Output Voltage TDAT VOL VBAT 2 4 V 0 05 x VBAT 0 07 x VBAT V High Level Output Voltage TDAT VOH VBAT 2 4 V 0 93 x VBAT 0 95 x VBAT V Low Level Input Current TDAT IIL VIL 0 V 0 mA High Level Input Current TDAT IIH VIH 4 V 0 05 0 3 mA High Level Output Current IOH TDAT 100 µA Low Level Output...

Page 72: ...00 kΩ 0 93 x VBAT 0 95 x VBAT V Rise and fall time tf CL 10 pF RL 100 kΩ VBAT 2 4 V 500 ns Parameter Sign Note Min Nom Max Unit Control Counter Clock Frequency fctrl fRES Hz Wake Pattern Waiting Count configurable cwait 1024 16384 Wake Pattern Waiting Time configurable twait fRES 134 2 kHz twait cwait fRES 7 6 122 1 ms Wake Pattern Waiting Count Resolution 4 bit Wake Pattern Receive Time fix value...

Page 73: ... MIL STD 883 compliant 4 2 4 20 Package The 3D Analog Front End IC is delivered in the following package 16 PIN TSSOP PW R PDSO G16 For more information about this package please refer to http www ti com sc docs psheets mechanic P htm Parameter Sign Note Min Nom Max Unit High Bit Detection Threshold Count PPM cHdet 8 64 128 High Bit Detection Threshold Time PPM tHdet fRES 134 2 kHz tHdet cHdet fRE...

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