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Analog Front End IC TMS37122 - Reference Guide
August ’01
The available voltage range depends on the voltage VCL, which can be charged into
CL during extended Wake-up Time and the minimum required supply voltage for the
oscillation maintenance circuit (Continuous Pluck Circuit). For proper function with
minimum 3 V should be calculated. Limitation of VCL can occur in worst case at 6
V. Therefore a VCL range of maximum 3 V should be defined.
The required capacitor is calculated with the following formulas:
Itot= Itx + IµC
CL [F] = Itot [A] * tTX[Sec] / dVCL [V]
Example:
Itot = 500µA
tTX = 15ms
dVCL = 3V
CL = Itot * tTX / dVCL = 2.5µF
If the capacitor Cbat is already in the µF range due to other reasons, CL can have less
capacity. It has only to supply the front-end part and the resonant circuit (IVCL). At a
quality factor of 10 at least a capacitor of 680nF will be required.
2.2.2.2
Test Mode
The resonant circuit of the Identification Device must be trimmed to optimum resonance after
assembly. Beside this the desired option bits must be configured in the 3D-AFE memory. For
this purpose a Test Interface is provided connected typically to Tester Unit. For engineering
purpose also a special Digital Interface Test Box, controlled by a PC via RS232 interface, can
be used (see Figure 8). Circuit diagrams for the Test Box can be delivered on request.
The Test Box is able to measure the oscillation frequency of each resonant circuit using sep-
arate test modes. During these tests VCL is fed with a stable voltage and the oscillation is trig-
gered via the test interface. The period duration is measured and reported via RS232 to the
PC. The voltage can either be supplied by a IEEE interface controlled power supply or by
power supplies in the Test Box.
