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SLVUB26C – May 2017 – Revised June 2018

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Copyright © 2017–2018, Texas Instruments Incorporated

Operating TPSM846C23 in Parallel

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Description

The TPSM846C23 is a PMBus™ enabled, synchronous buck power module designed to provide up to 35
A of output current. The TPSM846C23 can be paralleled with two devices to achieve output current up to
70 A. The TPSM846C23 is a highly-integrated, PMBus-enabled DC-DC power module that combines a
35-A DC/DC converter with power MOSFETs, a shielded inductor, some input and output capacitors, and
passives into a low profile package. The input voltage range is 4.5 V to 15 V. The output voltage range is
0.35 V to 2 V. The PMBus interface provides for converter configuration as well as monitoring of key
parameters including output voltage, output current, and the internal die temperature, as well as many
user-programmable configuration options.

This evaluation module is designed to demonstrate the ease-of-use and small printed-circuit-board area
that may be achieved when paralleling two TPSM846C23 power modules. Monitoring test points are
provided to allow measurement of efficiency, power dissipation, input ripple, output ripple, line and load
regulation, and transient response. Additionally, control test points are provided for use of the power good,
and synchronization features of the device. The EVM uses a recommended PCB layout that maximizes
thermal performance and minimizes output ripple and noise.

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Getting Started

Figure 1

highlights the user interface items associated with the EVM. The polarized input power terminal

block (TB1) is used for connection to the host input supply. TB2 and TB3 allow 4 terminals for VOUT and
TB4 and TB5 allow 4 terminals for PGND for connection to the load. These terminal blocks can except up
to 12 AWG wire.

Figure 1. EVM User Interface

The VIN Monitor (VIN and PGND) and VOUT Monitor (VS+ and VS–) test points located near the input
terminal block and the output terminal blocks are intended to be used as voltage monitoring points where
voltmeters can be connected to measure the input and output voltages.

Do not use these VIN and VOUT

monitoring test points as the input supply or output load connection points.

The PCB traces

connecting to these test points are not designed to support high currents.

Summary of Contents for TPSM846C23

Page 1: ...escription 2 2 Getting Started 2 3 Test Point Descriptions 4 4 Operation Notes 5 5 Performance Data 6 6 Schematic 7 7 Bill of Material 8 8 PCB Layout 9 List of Figures 1 EVM User Interface 2 2 Efficie...

Page 2: ...eling two TPSM846C23 power modules Monitoring test points are provided to allow measurement of efficiency power dissipation input ripple output ripple line and load regulation and transient response A...

Page 3: ...rface GUI to communicate and control the EVM To download the latest software visit http www ti com tool fusion_digital_power_designer The ALERT DATA CLK and CNTL test points are used to monitor and co...

Page 4: ...onse AGND Analog ground point Use any of the AGND test points as the ground reference for the control signals ALERT PMBus ALERT line used to monitor the ALERT signal CLK PMBus CLK line used to monitor...

Page 5: ...g frequency is required R23 must be removed from the clock circuit on the bottom of the EVM and an external clock must be connected to the EXT CLK test point The external clock applied to EXT CLK test...

Page 6: ...Power Dissipation W 0 10 20 30 40 50 60 70 0 2 4 6 8 10 12 14 16 18 D002 1 8 V 1 2 V 0 8 V Performance Data www ti com 6 SLVUB26C May 2017 Revised June 2018 Submit Documentation Feedback Copyright 201...

Page 7: ...38 VOUT 39 VOUT 40 VOUT 41 VOUT 55 PGND 33 PGND 54 VIN 45 VIN 44 ADDR0 17 PGND 56 PGND 57 VIN 46 DIFFO 6 VS 4 PGND 36 VIN 53 AGND 10 BP6_RTN 48 PGND 32 PGND 58 BP3 47 BP6 49 VINBP 50 ADDR1 16 U2 TPSM...

Page 8: ...nik J1 J2 2 Socket Strip 2x1 100mil Black Tin TH 310 43 102 41 001000 Mill Max P1 1 Header 2 54mm 5 2 Gold TH AWHW 10G 0202 T Assmann WSW P2 P4 2 Header 100mil 2 2 Tin TH PEC02DAAN Sullins Connector S...

Page 9: ...ntation Feedback Copyright 2017 2018 Texas Instruments Incorporated Operating TPSM846C23 in Parallel 8 PCB Layout Figure 6 through Figure 13 illustrate the EVM PCB layout images Figure 6 Top Component...

Page 10: ...7 Revised June 2018 Submit Documentation Feedback Copyright 2017 2018 Texas Instruments Incorporated Operating TPSM846C23 in Parallel Figure 10 Layer 4 Copper Figure 11 Layer 5 Copper Figure 12 Bottom...

Page 11: ...E Page numbers for previous revisions may differ from page numbers in the current version Changes from B Revision December 2017 to C Revision Page Corrected resistor references R18 and R23 5 Changes f...

Page 12: ...set forth above or credit User s account for such EVM TI s liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that...

Page 13: ...the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain great...

Page 14: ...t the EVM user guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the...

Page 15: ...OST OF REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF...

Page 16: ...TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD...

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