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Table of Contents

1 Introduction

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2 Setup

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3

2.1 LDO Input and Output Connector Descriptions..................................................................................................................

3

2.2 Optional Load Transient Input and Output Connector Descriptions...................................................................................

4

2.3 TPS7A57 LDO Operation...................................................................................................................................................

5

2.4 Optional Load Transient Circuit Operation.........................................................................................................................

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3 Board Layout

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4 TPS7A57EVM-056 Schematics

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5 Bill of Materials

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List of Figures

Figure 1-1. TPS7A57EVM-056 Evaluation Module.....................................................................................................................

1

Figure 2-1. TPS7A57EVM-056 Turn On......................................................................................................................................

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Figure 2-2. TPS7A57EVM-056 With Current Probe Attached.....................................................................................................

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Figure 2-3. TPS7A57EVM-056 Load Transient Results..............................................................................................................

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Figure 2-4. TPS7A57EVM-056 Load Transient Results With a Q1 MOSFET.............................................................................

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Figure 3-1. Top Assembly Layer and Silkscreen.........................................................................................................................

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Figure 3-2. Top Layer Routing.....................................................................................................................................................

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Figure 3-3. Layer 2......................................................................................................................................................................

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Figure 3-4. Layer 3......................................................................................................................................................................

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Figure 3-5. Layer 4....................................................................................................................................................................

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Figure 3-6. Layer 5....................................................................................................................................................................

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Figure 3-7. Bottom Layer Routing..............................................................................................................................................

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Figure 3-8. Bottom Assembly Layer and Silkscreen..................................................................................................................

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Figure 4-1. Schematic................................................................................................................................................................

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Figure 4-2. Load Transient Schematic.......................................................................................................................................

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Trademarks

LeCroy

 is a trademark of Teledyne LeCroy.

Kapton

®

 is a registered trademark of DuPont.

All trademarks are the property of their respective owners.

Table of Contents

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2

TPS7A57EVM-056 Evaluation Module

SBVU075 – APRIL 2022

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Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for TPS7A57EVM-056

Page 1: ...A57 low dropout linear regulator LDO Included in this user s guide are setup and operating instructions thermal and layout guidelines a printed circuit board PCB layout schematic diagrams and a bill o...

Page 2: ...ent Results 8 Figure 2 4 TPS7A57EVM 056 Load Transient Results With a Q1 MOSFET 8 Figure 3 1 Top Assembly Layer and Silkscreen 9 Figure 3 2 Top Layer Routing 9 Figure 3 3 Layer 2 9 Figure 3 4 Layer 3...

Page 3: ...A57 The header connects the REF pin to a resistor to set a given output voltage value The voltage options are 0 5 V 1 2 V 1 8 V 2 5 V 3 3 V 5 0 V 2 1 4 J4 EN J4 EN is a 3 pin header used to enable or...

Page 4: ...nt MOSFET drain voltage 2 2 4 IN1 IN1 is the connection for the function generator to drive the gate driver device IN1 is terminated by the 50 resistor R22 2 2 5 J15 J15 is a high frequency kelvin con...

Page 5: ...across the header to tie GND to EN or leaving the 3 pin header floating disables the device 3 Placing a 2 pin shunt across the header to tie GND to CP_EN disables the internal charge pump Alternativel...

Page 6: ...through these connectors In cases where very fast transient tests are performed ringing may occur on VIN or VOUT as a result of the parasitic inductance within the PCB of the EVM A strip of wire place...

Page 7: ...current limit As illustrated in Figure 2 3 the TPS7A57 transient response is very fast and the output voltage recovers in well under 1 ms after the initial load transient Therefore use a load transie...

Page 8: ...ad Transient Results Figure 2 4 TPS7A57EVM 056 Load Transient Results With a Q1 MOSFET Setup www ti com 8 TPS7A57EVM 056 Evaluation Module SBVU075 APRIL 2022 Submit Document Feedback Copyright 2022 Te...

Page 9: ...7 LDO LMG1020YFFR gate driver and pulsed resistors R10 R11 R12 R13 and R14 are most at risk of raising to a high junction temperature during normal operation Figure 3 1 Top Assembly Layer and Silkscre...

Page 10: ...r 5 Figure 3 7 Bottom Layer Routing Figure 3 8 Bottom Assembly Layer and Silkscreen Board Layout www ti com 10 TPS7A57EVM 056 Evaluation Module SBVU075 APRIL 2022 Submit Document Feedback Copyright 20...

Page 11: ...1 OUT 12 BIAS 5 CP_EN 15 EN 16 NR SS 8 PG 14 REF 7 SNS 13 Thermal_Pad 17 GND 6 TPS7A5701RTET U1 CP_EN EN Vbias Vin GND REF NR 4 7 F 16V C10 Vout TP7 2 00M R2 2 00M R3 TP1 22 F 10V C5 6 3V 1uF C6 10uF...

Page 12: ...3202Q2 0 R25 R13 R14 R12 R11 R10 R17 R18 R19 R16 R20 J7 J8 Drain Gate 1 2 3 4 5 J15 100V 1pF C11 0 R15 50V 0 015uF C16 1 00k R24 50V 10uF C14 50V 10uF C13 50V 0 1uF C12 TP13 Figure 4 2 Load Transient...

Page 13: ...to buy or mount N A N A N A J1 1 Header 100mil 2x1 Tin SMD SMD 2 Leads Body 200x100mil TSM 102 01 T SV P TR Samtec J2 1 Jumper SMT shorting jumper SMT JMP 36 30X40SMT Any J3 1 Header 2 54mm 6x2 Gold S...

Page 14: ...uF 6 3 V 10 X7R 0402 402 GRM155R70J105K A12D MuRata C8 0 10uF CAP CERM 10 uF 25 V 10 X7R 0805 805 GRM21BZ71E106K E15L MuRata C11 0 1pF CAP CERM 1 pF 100 V 5 C0G NP0 0805 805 GQM2195C2A1R0 CB01D MuRat...

Page 15: ...12 TP13 0 Test Point Compact SMT Testpoint_Keystone _Compact 5016 Keystone U2 0 5V 7A 5A Low Side GaN Driver With 60MHz 1ns Speed YFF0006AEAE DSBGA 6 YFF0006AEAE LMG1020YFFR Texas Instruments LMG1020Y...

Page 16: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 17: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 18: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 19: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 20: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 21: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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