Texas Instruments TPS6594-Q1 Series, User Manual

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EVM Details
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6 SLVUBT0 – December 2019
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TPS6594x-Q1 Evaluation Module
3.3 Configuration Headers
There are five headers available to configure the EVM function. Headers J26 and J37 configure the
backup power supply and master and slave mode of operation, respectively. Header J7, as shown in the
silk screen picture in
Figure 2 , is used to configure the EVM to match the feature setting written to the
TPS6594x-Q1 configuration registers. J30 is used to select the PMIC IO voltage, either 1.8 V or 3.3 V.
The fifth header is a portion of J15 which allows VSYS to be powered from the USB connection and the
configuration of GPIO1.
Figure 2. EVM Header J7
Table 4. Header J7 Description
Option Pins Configuration Description
SPI_EN Open (Default) I
2
C Mode. The signal path for I
2
C communication between the
MCU and the PMIC is enabled.
Closed SPI mode. The signal path for SPI communication between the
MCU and the PMIC is enabled.
TRIG_WDG, GPIO2,
SDA2/SDO Open GPIO mode. GPIO2 from PMIC is connected to PM7 of the MCU
through a level translator.
TRIG_WDG, GPIO2: Closed Trigger Watchdog mode. GPIO2 of the PMIC should be in the
Alternative function to support the watchdog trigger input signal.
GPIO2 from the PMIC is connected to the MCU output and
TRIG_WDG.
GPIO2,SDA2/SDO: Closed
(Default) I
2
C Mode (J7 VIO_IN, I2C/SPI:
Open)
Q&A Watchdog mode. GPIO2
of the PMIC should be in the
Alternative function to support
the Q&A Watchdog and the I
2
C
mode is selected. This setting
is done in conjunction with J15,
GPIO1,SCL2/CS: Closed.
SPI mode (J7 VIO_IN, I2C/SPI:
Closed) SPI mode, Chip Select. GPIO2
of the PMIC should be in the
Alternative function to support
SPI communication. This
setting is done in conjunction
with J15, GPIO1, SCL2/CS:
Closed.
ERR_SoC, GPIO3 Open (Default) GPIO mode. GPIO3 of the PMIC is connected to PP5 of the
through a level translator.
Closed SoC Error Count Down mode. GPIO3 of the PMIC should be in
the Alternative function to support the system error count down
from the SoC. GPIO is connected to alternative MCU output,
nERR_SoC.