Texas Instruments TPS65120EVM-076, User Manual

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Input/Output Connections
2-2
2.1 Input/Output Connections
The EVM’s input and output connections are described in the following
paragraphs.
-
J1-VIN − This header connects to the positive terminal of the input power
supply.
-
J2-GND − This header connects to the negative terminal of the input pow-
er supply.
-
J3-VGH − This header is the output terminal for the boosted gate voltage,
VGH.
-
J4-GND − This header is a GND terminal.
-
J7-GND − This header is a GND terminal.
-
J8-VGL − This header is the output terminal for the inverted gate voltage,
VGL.
-
J9-VMAIN − This header is the output terminal for the main voltage,
VMAIN.
-
J10-GND − This header is a GND terminal.
-
J11-BOOT − This header is measurement/sense point for the bootstrap
voltage, BOOT.
-
JP1-EN − The middle pin of this jumper connects to the EN pin on the IC.
Tying this pin to VIN enables VMAIN on the IC. Tying this pin to GND dis-
ables VMAIN on the IC.
-
JP2-RUN − The middle pin of this jumper connects to the RUN pin on the
IC. Tying this pin to VIN begins the power−up procedure of the IC. Tying
this pin to GND disables the IC.
-
JP5-LDOIN on TPS65120EVM or VGL on TPS65123EVM
For the TPS65120EVM, the middle pin of this jumper is a measurement/
sense point for the input to the auxiliary LDO and pin 3 is GND. LDOIN is
connected to BOOT through 0−
Ω
resistor R7. Pin 1 is floating.
For the TPS65124EVM, the middle pin of this jumper connects to VGL pin
on the IC. Tying this pin to ON enables VGL; tying it to OFF disables VGL.
-
JP6−LDOOUT on TPS65120EVM or VGH on TPS65124EVM
For the TPS65120EVM, the middle pin of this jumper is the output for the
auxiliary linear regulator, and pin 3 is GND. Pin 1 is floating.
For the TPS65124EVM, the middle pin of this jumper connects to VGH pin
on the IC. Tying this pin to ON enables VGH. Tying this pin to OFF disables
VGH.
The headers and jumpers that were omitted in the previous discussion are
not populated on the EVM and are discussed in section 1.3.