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Background
1-2
1.1
Background
The TPS65100EVM uses a TPS65100 multichannel output IC to provide three
LCD power rails, as well as a linear regulator controller to provide 3.3 V and
a VCOM buffer. The goal of the EVM is to facilitate evaluation of the
TPS65100.
1.2
Performance Specification Summary
Table
1−1 provides a summary of the TPS65100EVM performance
specifications. All specifications are given for an ambient temperature of 25
°
C.
Table 1−1. Typical Performance Specification Summary for VIN = 3.3 V and VOUT1 = 10 V,
T
A
= 25
°
C
Specification
Voltage Range
(V)
Current Range
(mA)
Specification
Min
Typ
Max
Min
Typ
Max
VIN
2.7
3.3
4.0
3000
VOUT1
9.85
10
10.15
0
300
VOUT2
−5.10
−5
−4.90
0
20
(1)
VOUT3
22.5
23
23.5
0
20
(1)
VOUT4
N/A
(2)
N/A
VCOM
4.92
5
5.07
0
650 peak
(1)
1) Maximum currents are determined by ambient conditions.
2) The linear regulator requires VIN
≥
3.7 V for normal operation and should
be disabled using JP3.
1.3
Modifications
The primary goal of this EVM is to facilitate user evaluation of the TPS65100.
To facilitate user customization of the EVM, the board was designed with
devices having 603 or larger footprints. So, a real implementation would likely
occupy less total board space.
Changing components can improve or degrade EVM performance. For
example, using an inductor with larger dc resistance for the main boost
converter will lower efficiency of the solution. In addition, using a BJT with
lower Beta or in a smaller package will limit the total output current that the
linear regulator can provide.
The main boost converter requires external compensation components (R7,
C11) for stability. This EVM has been optimized for an input voltage of 3.3 V.
If a different input voltage and/or a different output voltage is to be applied, the
main boost converter needs to be re-compensated in order to be stable over
the entire load and temperature range (see Table 1−2 and Table 4−2).
Summary of Contents for TPS65100EVM-030
Page 1: ...TPS65100EVM 030 February 2004 PMP Portable Power User s Guide SLVU101...
Page 6: ...iv...
Page 12: ...Modifications 1 4 This page has been left blank intentionally...
Page 20: ...Layout 3 3 Board Layout Figure 3 3 Bottom Layer Routing...
Page 21: ...Layout 3 4 This page has been left blank intentionally...