Texas Instruments TPS65053EVM-389 User Manual Download Page 3

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J12 - VOUT DCDC2

J12 - VOUT DCDC2

This header is the positive output of VDCDC2 step-down converter. This output is externally adjustable for
the TPS65053 and is programmed to a value of 1.8-V on the EVM. VDCDC2 is capable of sourcing up to
600-mA. A load can be connected between J12 and J13 (GND). Applications using Freescale™ i.MX27
can can utilize J12-VOUT DCDC2 to power the QVDD rail of the i.MX27 processor.

J13 - GND

J13 is the return connection of VOUT VDCDC2 output rail. A load can be connected between J13 and J12
(VOUT DCDC2).

JP1 - VIN_LDO1

JP1 selects the input voltage source for LDO1.

Place a shorting bar in the VOUT_DCDC1 position to select the output of VDCDC1 converter as input
voltage source for LDO1.

Place a shorting bar in the VIN position to select the input voltage as input source for LDO1.

JP2 - VIN_LDO2/3

JP2 selects the input voltage source for LDO2 and LDO3.

Place a shorting bar in the VOUT_DCDC1 position to select the output of VDCDC1 converter as input
voltage source for LDO2 and LDO3.

Place a shorting bar in the VIN position to select the input voltage as input source for LDO2 and LDO3.

JP3 - EN_LDO1

Placing a shorting bar between EN LDO1 and ON ties the EN pin of LDO1 to VIN, thereby enabling LDO1.
Placing a shorting bar between EN LDO1 and OFF ties the EN pin of LDO1 to GND, thereby disabling
LDO1.

JP4 - EN_DCDC2

Placing a shorting bar between EN_DCDC2 and ON ties the EN pin of DCDC2 to VIN, thereby enabling
DCDC2. Placing a shorting bar between EN_DCDC2 and OFF ties the EN pin of DCDC2 to GND, thereby
disabling DCDC2.

JP5 - EN_DCDC1

Placing a shorting bar between EN_DCDC1 and ON ties the EN pin of DCDC1 to VIN, thereby enabling
DCDC1. Placing a shorting bar between EN_DCDC1 and OFF ties the EN pin of DCDC1 to GND, thereby
disabling DCDC1.

JP6 - MODE Input

JP6 selects the forced PWM or Power Save Mode (PSM) operation for the switching converters DCDC1
and DCDC2.

Placing a shorting bar between MODE and PWM ties the MODE pin of TPS65053 to VIN, thereby
selecting forced PWM operating mode for the DCDC converters. Placing a shorting bar between MODE
and PSM (Power Save Mode) ties the MODE pin of TPS65053 to GND, thereby selecting Power Save
Mode operating mode for the DCDC converters at light-load conditions. If Power Save Mode is selected
the DCDC converters will automatically switch to PWM mode at havier load conditions.

JP7 - EN_LDO2

Placing a shorting bar between EN LDO2 and ON ties the EN pin of LDO2 to VIN, thereby enabling LDO2.
Placing a shorting bar between EN LDO2 and OFF ties the EN pin of LDO2 to GND, thereby disabling
LDO2.

JP8 - EN_LDO3

Placing a shorting bar between EN LDO3 and ON ties the EN pin of LDO3 to VIN, thereby enabling LDO3.
Placing a shorting bar between EN LDO3 and OFF ties the EN pin of LDO3 to GND, thereby disabling
LDO3.

SLVU262 – February 2009

TPS65053EVM-389

3

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Summary of Contents for TPS65053EVM-389

Page 1: ...10 The Texas Instruments TPS65053EVM 389 evaluation module EVM enables designers to evaluate the operation and performance of the TPS65053 Power Management Integrate Circuit PMIC for applications tha...

Page 2: ...f supplying up to 200 mA A load can be connected between J5 and J6 GND J6 GND J6 is the return connection of VLDO3 output rail A load can be connected between J6 and J5 VLDO3 J7 RESET This header allo...

Page 3: ...g LDO1 JP4 EN_DCDC2 Placing a shorting bar between EN_DCDC2 and ON ties the EN pin of DCDC2 to VIN thereby enabling DCDC2 Placing a shorting bar between EN_DCDC2 and OFF ties the EN pin of DCDC2 to GN...

Page 4: ...53EVM Voltage VDCDC1 2 7 V VDCDC2 1 4 V VLD01 1 8 V VLD02 1 4 V VLD03 1 3 V Table 2 Maximum Load Current Maximum Load TPS65053EVM Current VDCDC1 1 A VDCDC2 600 mA VLD01 400 mA VLD02 200 mA VLD03 200 m...

Page 5: ...tage to J10 4 Connect all loads to the outputs 5 Turn on input voltage Table 3 Factory EVM Jumper Settings Shunt Location Jumper TPS65053EVM JP1 Between VOUT_DCDC1 and VIN_LDO1 JP2 Between VOUT_DCDC1...

Page 6: ...yout www ti com This chapter provides the TPS65053EVM 389 board layout and illustrations Figure 2 and Figure 3 show the board layout for the TPS65053EVM 389 PWB Figure 2 Assembly Layer 6 TPS65053EVM 3...

Page 7: ...www ti com Board Layout Figure 3 Top Layer Routing SLVU262 February 2009 TPS65053EVM 389 7 Submit Documentation Feedback...

Page 8: ...aterials Schematic and Bill of Materials www ti com Figure 4 Bottom Layer Routing This chapter provides the TPS65053EVM 389 schematic and bill of materials 8 TPS65053EVM 389 SLVU262 February 2009 Subm...

Page 9: ...4 1 Schematic www ti com Schematic and Bill of Materials Figure 5 TPS65053EVM 389 Schematic SLVU262 February 2009 TPS65053EVM 389 9 Submit Documentation Feedback...

Page 10: ...ng Any x 2 JP1 JP2 JP3 JP4 0 100 inch 8 Header 3 pin 100mil spacing Any JP5 JP6 JP7 JP8 x 3 0 118 x 2 L1 L2 2 2uH Inductor SMT 1 5A 110milliohm LPS3015 222ML Coilcraft 0 118 inch 1 R1 562k Resistor Ch...

Page 11: ...or to handling the product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the...

Page 12: ...ce TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonabl...

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