Texas Instruments TPS65053EVM-389 User Manual Download Page 2

2

Setup

2.1

Input/Output Connector Descriptions

Setup

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This chapter describes the jumpers and connectors on the EVM, as well as how to properly connect,
setup, and use the TPS65053EVM-389.

J1 - VLDO1

This header is the positive output of LDO1 linear regulator. This output is externally adjustable for the
TPS65053 and is programmed to a value of 1.8 V on the EVM. The VLDO1 output is capable of supplying
up to 400-mA. A load can be connected between J1 and J2 (GND). Applications using Freescale™
i.MX27 can utilize J1-VLDO1 to power the NVDD_DDR, analog, and FUSEVDD rails of the i.MX27
processor.

J2 - GND

J2 is the return connection of VLDO1 output rail. A load can be connected between J2 and J1 (VLDO1).

J3 - VLDO2

This header is the positive output of LDO2 linear regulator. This output is externally adjustable for the
TPS65053 and is programmed to a value of 1.4 V on the EVM. The VLDO2 output is capable of supplying
up to 200 mA. A load can be connected between J3 and J4 (GND). Applications using Freescale™ i.MX27
can utilize J3-VLDO2 to power the RTCVDD and OSC32VDD rails of the i.MX27 processor.

J4 - GND

J4 is the return connection of VLDO2 output rail. A load can be connected between J4 and J3 (VLDO2).

J5 - VLDO3

This header is the positive output of LDO3 linear regulator. This output is fixed at 1.3 V for the TPS65053.
The VLDO3 output is capable of supplying up to 200-mA. A load can be connected between J5 and J6
(GND).

J6 - GND

J6 is the return connection of VLDO3 output rail. A load can be connected between J6 and J5 (VLDO3).

J7 - RESET

This header allows the user to monitor the RESET output. The RESET output goes high 100-ms after the
THRESHOLD input exceeds 1.0-V. RESET goes low when the THRESHOLD input falls below 1.0-V. On
the EVM, the RESET circuitry monitors the outputs VOUT DCDC1 and VOUT DCDC2.

J8 - VOUT DCDC1

This header is the positive output of VDCDC1 step-down converter. This output is externally adjustable for
the TPS65053 and is programmed to a value of 2.7-V on the EVM. VDCDC1 is capable of sourcing up to
1.0-A. A load can be connected between J8 and J9 (GND). Applications using Freescale™ i.MX27 can
utilize J8-VOUT DCDC1 to power NVDD_FAST, NVDD_SLOW, and OSC26VDD of the i.MX27 processor.

J9 - GND

J9 is the return connection of VOUT VDCDC1 output rail. A load can be connected between J9 and J8
(VOUT DCDC1).

J10 - VIN

This header is the positive connection to the input power supply. The power supply must be connected
between J10 and J11 (GND). The leads to the input supply should be twisted and kept as short as
possible. The input voltage has to be between 2.5-V and 6-V.

J11 - GND

This header is the return connection to the input power supply. Connect the power supply between J11
and J10 (VIN). The leads to the input supply should be twisted and kept as short as possible. The input
voltage has to be between 2.5-V and 6-V.

TPS65053EVM-389

2

SLVU262 – February 2009

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Summary of Contents for TPS65053EVM-389

Page 1: ...10 The Texas Instruments TPS65053EVM 389 evaluation module EVM enables designers to evaluate the operation and performance of the TPS65053 Power Management Integrate Circuit PMIC for applications tha...

Page 2: ...f supplying up to 200 mA A load can be connected between J5 and J6 GND J6 GND J6 is the return connection of VLDO3 output rail A load can be connected between J6 and J5 VLDO3 J7 RESET This header allo...

Page 3: ...g LDO1 JP4 EN_DCDC2 Placing a shorting bar between EN_DCDC2 and ON ties the EN pin of DCDC2 to VIN thereby enabling DCDC2 Placing a shorting bar between EN_DCDC2 and OFF ties the EN pin of DCDC2 to GN...

Page 4: ...53EVM Voltage VDCDC1 2 7 V VDCDC2 1 4 V VLD01 1 8 V VLD02 1 4 V VLD03 1 3 V Table 2 Maximum Load Current Maximum Load TPS65053EVM Current VDCDC1 1 A VDCDC2 600 mA VLD01 400 mA VLD02 200 mA VLD03 200 m...

Page 5: ...tage to J10 4 Connect all loads to the outputs 5 Turn on input voltage Table 3 Factory EVM Jumper Settings Shunt Location Jumper TPS65053EVM JP1 Between VOUT_DCDC1 and VIN_LDO1 JP2 Between VOUT_DCDC1...

Page 6: ...yout www ti com This chapter provides the TPS65053EVM 389 board layout and illustrations Figure 2 and Figure 3 show the board layout for the TPS65053EVM 389 PWB Figure 2 Assembly Layer 6 TPS65053EVM 3...

Page 7: ...www ti com Board Layout Figure 3 Top Layer Routing SLVU262 February 2009 TPS65053EVM 389 7 Submit Documentation Feedback...

Page 8: ...aterials Schematic and Bill of Materials www ti com Figure 4 Bottom Layer Routing This chapter provides the TPS65053EVM 389 schematic and bill of materials 8 TPS65053EVM 389 SLVU262 February 2009 Subm...

Page 9: ...4 1 Schematic www ti com Schematic and Bill of Materials Figure 5 TPS65053EVM 389 Schematic SLVU262 February 2009 TPS65053EVM 389 9 Submit Documentation Feedback...

Page 10: ...ng Any x 2 JP1 JP2 JP3 JP4 0 100 inch 8 Header 3 pin 100mil spacing Any JP5 JP6 JP7 JP8 x 3 0 118 x 2 L1 L2 2 2uH Inductor SMT 1 5A 110milliohm LPS3015 222ML Coilcraft 0 118 inch 1 R1 562k Resistor Ch...

Page 11: ...or to handling the product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the...

Page 12: ...ce TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonabl...

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