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Setup

Table 1. Performance Specification Summary (continued)

SPECIFICATION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Maximum efficiency

V

IN

= 3.6V, V

OUT

= 1.7V, I

OUT

= 750mA

91.4%

2

Setup

This section describes the jumpers and connectors on the EVM as well as how to properly connect, set
up, and use the TPS6236xEVM-655.

2.1

Connector/Jumper Descriptions

2.1.1

J1

V

IN

This header is for the positive input supply voltage to the converter. The leads to the input supply should
be twisted and kept as short as possible to minimize EMI transmission and reduce inductive voltage droop
at a load transient event. This voltage should be between 2.5V and 5.5V.

2.1.2

J2

S+/S-

Sense connector for V

IN

. Connect input supply's sense leads to this point. Monitor the V

IN

voltage at this

point.

2.1.3

J3

GND

This is the return connection for the input power supply of the converter. The leads to the input supply
should be twisted and kept as short as possible to minimize EMI transmission and reduce inductive
voltage droop at a load transient event.

2.1.4

J4

V

OUT

This header connects to V

OUT

. Connect the load (processor) at this point if the load current will remain

below 1A. If the load current will exceed 1A, use terminal block J7 instead. The leads to the load should
be twisted and kept as short as possible to minimize EMI transmission and reduce inductive voltage droop
at a load transient event.

2.1.5

J5

SNS+/SNS-

Remote sense connector for the IC. For proper regulation, this must be connected at the load. This is
a high impedance connection back to the TPS6236x's remote sense inputs and is required for output
regulation. Monitor the output voltage at this point.

2.1.6

J6

GND

This is the return connection for the load. If the load current will exceed 1A, do not use headers J4 and J6,
but use terminal block J7 instead. The leads to the load should be twisted and kept as short as possible to
minimize EMI transmission and reduce inductive voltage droop at a load transient event.

2.1.7

J7

V

OUT

/GND Terminal Block

This terminal block should be used to connect to the load (processor) if the load current will exceed 1A. If
the load current will remain below 1A, the J4/J6 headers may be used instead. The leads to the load
should be twisted and kept as short as possible to minimize EMI transmission and reduce inductive
voltage droop at a load transient event.

2.1.8

J8

I

2

C Connection from USB-TO-GPIO Adaptor

This connects the USB-TO-GPIO adaptor to the TPS6236xEVM-655. It provides the I

2

C signals and a

3.3V supply for powering V

DD

. If the USB-TO-GPIO adaptor is not used, do not connect to J8, but connect

the I

2

C signals to the J9 header instead. This connector is keyed to prevent incorrect installation.

3

SLVU425A

April 2011

Revised July 2011

TPS6236xEVM-655

Submit Documentation Feedback

Copyright

©

2011, Texas Instruments Incorporated

Summary of Contents for TPS6236 EVM-655 Series

Page 1: ...Efficiency vs Input Voltage IOUT 1 5A VOUT 1 4V 9 3 Efficiency vs Output Current VIN 3 6V VOUT 0 92 1 16 1 4 1 7 9 4 Load Regulation VOUT 1 4V VIN 3 6V 10 5 Line Regulation VOUT 1 4V IOUT 1 5A 10 6 S...

Page 2: ...can be downloaded from the TPS6236xEVM 655 Product Page located at http focus ti com docs toolsw folders print tps62360evm 655 html Printed Circuit Board Assembly The board contains the either the TPS...

Page 3: ...ssion and reduce inductive voltage droop at a load transient event 2 1 5 J5 SNS SNS Remote sense connector for the IC For proper regulation this must be connected at the load This is a high impedance...

Page 4: ...n to either a logic high jumper across pins 1 and 2 or a logic low jumper across pins 2 and 3 2 1 14 JP4 EN This jumper sets the EN pin to either a logic high jumper across pins 1 and 2 or a logic low...

Page 5: ...ctors on the ribbon cable are keyed to prevent incorrect installation Connect the load processor to either the output headers J4 and J6 for currents below 1A or to the output terminal block J7 for cur...

Page 6: ...adapter and PC as instructed during the install process The host PC software also automatically searches on the Internet if connected for updates to the EVM software If a new update is available the s...

Page 7: ...tware SET0 SET3 section correspond to registers 0x00h thought 0x03h in the TPS6236x These registers set the target output voltage and operating mode PFM PWM or forced PWM The output voltage on the TPS...

Page 8: ...that can be measured by high impedance measurement equipment such as an oscilloscope The op amp U2 is powered from the USB TO GPIO adaptor The USB TO GPIO adaptor must be installed for the output vol...

Page 9: ...Efficiency www ti com Test Results 5 Test Results This section provides typical performance waveforms for the TPS6236xEVM 655 Figure 2 Efficiency vs Input Voltage IOUT 1 5A VOUT 1 4V Figure 3 Efficie...

Page 10: ...04 0 06 0 08 0 1 2 5 3 3 5 4 4 5 5 5 5 V Input Voltage V I Line Regulation Test Results www ti com Figure 4 Load Regulation VOUT 1 4V VIN 3 6V Figure 5 Line Regulation VOUT 1 4V IOUT 1 5A 10 TPS6236xE...

Page 11: ...A div EN VOUT Iinductor www ti com Test Results Figure 6 Start up VIN 3 6V VOUT 1 4V IOUT 1 5A Figure 7 Shutdown VIN 3 6V VOUT 1 4V IOUT 0 output cap discharge enabled 11 SLVU425A April 2011 Revised...

Page 12: ...iv 5 V div SW Iinductor V AC COUPLED IN Test Results www ti com Figure 8 Output Voltage Ripple VIN 3 6V VOUT 1 4V IOUT 3A Figure 9 Input Voltage Ripple VIN 3 6V VOUT 1 4V IOUT 3A 12 TPS6236xEVM 655 SL...

Page 13: ...ti com Test Results Figure 10 Load Transient Response VIN 3 6V VOUT 1 4V IOUT 1A to 2A step Figure 11 Thermal Performance VIN 3 6V VOUT 1 4V IOUT 3A 13 SLVU425A April 2011 Revised July 2011 TPS6236xEV...

Page 14: ...ort as possible to minimize trace inductance Careful attention has been given to the routing of high frequency current loops and a single point grounding scheme is used Also the majority of the heatsi...

Page 15: ...www ti com Board Layout Figure 13 Top Layer Figure 14 Layer 2 15 SLVU425A April 2011 Revised July 2011 TPS6236xEVM 655 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated...

Page 16: ...Board Layout www ti com Figure 15 Layer 3 Figure 16 Bottom Layer 16 TPS6236xEVM 655 SLVU425A April 2011 Revised July 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated...

Page 17: ...materials is provided in two tables Table 3 are the components required to build the TPS6236x solution Table 4 are the components used only to evaluate the TPS6236xEVM 655 solution 7 1 Schematic Figur...

Page 18: ...F Capacitor Ceramic 10V X5R 20 0402 Std Std 1 1 1 1 C3 100 F Capacitor Ceramic 6 3V X5R 20 1210 Std Std 0 0 0 0 C7 C10 C11 Open Capacitor Ceramic 6 3V X5R 20 0805 Std Std 0 0 0 0 C8 C9 Open Capacitor...

Page 19: ...ct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer...

Page 20: ...orized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parti...

Page 21: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TPS62360EVM 655 TPS62361BEVM 655 TPS62362EVM 655...

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