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5 Board Layout
This section provides a description of the TPS56C20EVM-614, PCB layout, and layer illustrations.
5.1 Board Layout
through
show the board layout for the TPS56C20EVM-614. The top layer contains the
main power traces for PVIN, VIN, VOUT, SWITCH node, and a huge area filled with ground. Many of the signal
traces are also located on the top side. The design locates the input decoupling capacitors and the voltage set
point resistor divider network components as close to the IC as possible. The input and output connectors, test
points, and most of the components are located on the top side. The analog ground (which is used as a return
for the I2C interface signals) connects to the power ground at only one point on the top layer. Internal layer 1 and
internal layer 2 are filled with power ground. The bottom layer contains a few traces like the I2C connections and
the output voltage trace to the J3 connector.
Figure 5-1. Top Assembly
Board Layout
SBAU227A – MARCH 2014 – REVISED JUNE 2021
TPS56C20 Buck Converter Evaluation Module User's Guide
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