background image

TPS54810

SLVS420B 

 MARCH 2002 

 R EVISED FEBRUARY 2005

4-V TO 6-V INPUT, 8-A OUTPUT SYNCHRONOUS BUCK PWM

SWITCHER WITH INTEGRATED FETS (SWIFT

)

6,4 mm X 9,7 mm

 

FEATURES

D

30-m

 MOSFET Switches for High Efficiency

at 8-A Continuous Output

D

0.9-V to 3.3-V Adjustable Output Voltage

Range With 1% Accuracy

D

Externally Compensated

D

Fast Transient Response

D

Wide PWM Frequency:

Fixed 350 kHz, 550 kHz or 

Adjustable 280 kHz to 700 kHz

D

Load Protected by Peak Current Limit and

Thermal Shutdown

D

Integrated Solution Reduces Board Area and

Total Cost

APPLICATIONS

D

Low-Voltage, High-Density Systems With

Power Distributed at 5 V

D

Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs and

Microprocessors

D

Broadband, Networking, and Optical

Communications Infrastructure

D

Portable Computing/Notebook PCs

DESCRIPTION

As a member of the SWIFT

 family of dc/dc regulators,

the TPS54810 low-input voltage high-output current

synchronous buck PWM converter integrates all

required active components. Included on the substrate

with the listed features are a true, high performance,

voltage error amplifier that enables maximum

performance under transient conditions and flexibility in

choosing the output filter L and C components; an

under-voltage-lockout circuit to prevent start-up until

the input voltage reaches 3.8 V; an internally or

externally set slow-start circuit to limit in-rush currents;

and a power good output useful for processor/logic

reset, fault signaling, and supply sequencing.
The TPS54810 is available in a thermally enhanced

28-pin TSSOP (PWP) PowerPAD

 package, which

eliminates bulky heatsinks. TI provides evaluation

modules and the SWIFT

 designer software tool to aid

in quickly achieving high-performance power supply

designs to meet aggressive equipment development

cycles.

VSENSE

VIN

PH

BOOT
PGND

Output

COMP

AGND

VBIAS

Input

TPS54810

SIMPLIFIED SCHEMATIC

VSENSE

Compensation Network

I

L

 

 Load Current 

 A

Efficiency 

 %

EFFICIENCY AT 700 HZ

50

55

60

65

70

75

80

85

90

95

100

0

1

2

3

4

5

6

7

8

9

10

V

I

 = 5 V

V

O

 = 3.3 V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.

Copyright 

©

 2002, Texas Instruments Incorporated

PowerPAD and SWIFT are trademarks of Texas Instruments.

Summary of Contents for TPS54810

Page 1: ...tput filter L and C components an under voltage lockout circuit to prevent start up until the input voltage reaches 3 8 V an internally or externally set slow start circuit to limit in rush currents and a power good output useful for processor logic reset fault signaling and supply sequencing The TPS54810 is available in a thermally enhanced 28 pin TSSOP PWP PowerPAD package which eliminates bulky...

Page 2: ...GND 0 3 V Operating virtual junction temperature range TJ 40 to 125 C Storage temperature Tstg 65 to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 300 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated ...

Page 3: ...3 IL 4 A fs 350 kHz TJ 85 C 0 04 V Line regulation 1 3 IL 4 A fs 550 kHz TJ 85 C 0 04 V Load regulation 1 3 IL 0 A to 8 A fs 350 kHz TJ 85 C 0 03 A Load regulation 1 3 IL 0 A to 8 A fs 550 kHz TJ 85 C 0 03 A OSCILLATOR Internally set free running frequency range SYNC 0 8 V RT open 280 350 420 kHz Internally set free running frequency range SYNC 2 5 V RT open 440 550 660 kHz RT 180 kΩ 1 resistor to...

Page 4: ... hysteresis voltage SS ENA 1 0 03 V Falling edge deglitch SS ENA 1 2 5 µs Internal slow start time 2 6 3 35 4 1 ms Charge current SS ENA SS ENA 0V 3 5 8 µA Discharge current SS ENA SS ENA 1 3 V VI 1 5 V 1 5 2 3 4 0 mA POWER GOOD Power good threshold voltage VSENSE falling 90 Vref Power good hysteresis voltage 1 3 Vref Power good falling edge deglitch 1 35 µs Output saturation voltage PWRGD I sink ...

Page 5: ...PWRGD 4 Power good open drain output High Z when VSENSE 90 Vref otherwise PWRGD is low Note that output is low when SS ENA is low or the internal shutdown signal is active RT 28 Frequency setting resistor input Connect a resistor from RT to AGND to set the switching frequency When using the SYNC pin set the RT value for a frequency at or slightly lower than the external oscillator frequency SS ENA...

Page 6: ...e 3 35 ms Reference VREF 0 891 V Error Amplifier Thermal Shutdown 150 C SHUTDOWN SS_DIS PWM Comparator OSC Leading Edge Blanking 100 ns R Q S Adaptive Dead Time and Control Logic SHUTDOWN 30 mΩ VIN REG VBIAS VIN BOOT VIN PH CO PGND PWRGD Falling Edge Deglitch 35 µs VSENSE SHUTDOWN 0 90 Vref Hysteresis 0 03 Vref Powergood Comparator AGND VBIAS ILIM Comparator 3 6 V VO SYNC RT COMP VSENSE SS ENA TPS...

Page 7: ...k RT 180 k Figure 4 0 885 0 887 0 889 0 891 0 893 0 895 40 0 25 85 125 TJ Junction Temperature C Voltage Reference V VOLTAGE REFERENCE vs JUNCTION TEMPERATURE V ref 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 0 1 2 3 4 5 6 7 8 IL Load Current A Device Power Losses W DEVICE POWER LOSSES vs LOAD CURRENT TJ 125 C fs 700 kHz VI 5 V Figure 5 Figure 6 VI Input Voltage V OUTPUT VOLTAGE REGULATION vs INPUT VOLTAGE Ou...

Page 8: ...10 µF ceramic capacitor Taiyo Yuden C12 also a 10 µF ceramic capacitor Taiyo Yuden provides high frequency decoupling of the TPS54810 from the input supply and must be located as close as possible to the device Ripple current is carried in both C10 and C12 and the return path to PGND should avoid the current circulating in the output capacitors C5 C7 and C8 FEEDBACK CIRCUIT The values for these co...

Page 9: ...onnecting them to the ground area under the device as shown The only components that tie directly to the power ground plane are the input capacitors the output capacitors the input voltage decoupling capacitor and the PGND pins of the TPS54810 Use a separate wide trace for the analog ground signal path The analog ground is used for the voltage set point divider timing resistor RT slow start capaci...

Page 10: ...AS VIN VIN VIN VIN VIN PGND PGND PGND PGND PGND VOUT PH VIN TOPSIDE GROUND AREA VIAto Ground Plane ANALOG GROUND TRACE EXPOSED POWERP AD AREA COMPENSA TION NETWORK OUTPUT INDUCTOR OUTPUT FILTER CAPACITOR BOOT CAPACITOR INPUT BYPASS CAPACITOR INPUT BULK FILTER FREQUENCY SET RESISTOR SLOW ST ART CAPACITOR BIAS CAP ACITOR Figure 10 PCB Layout ...

Page 11: ...rough the vias Eight vias should be in the PowerPAD area with four additional vias located under the device package The size of the vias under the package but not in the exposed thermal pad area can be increased to 0 018 Additional vias beyond the twelve recommended that enhance thermal performance should be included in areas not under the device package Connect Pin 1 to Analog Ground Plane in Thi...

Page 12: ... 5 7 5 9 0 A 4 A 8 A VI Input Voltage V Line Regulation LINE REGULATION vs INPUT VOLTAGE VI 5 V VO 1 8 V TA 25 C fs 700 kHz Figure 15 25 35 45 55 65 75 85 95 105 115 125 0 1 2 3 4 Ambient Temperature AMBIENT TEMPERATURE vs OUTPUT CURRENT 1 IO Output Current A C T A 5 6 7 8 VI 5 V TJ 25 C fs 700 kHz Figure 16 t Time 1 µs div Output Ripple Voltage 10 mV div OUTPUT RIPPLE VOLTAGE VI 5 V VO 1 8 V IO 6...

Page 13: ...h a stable supply voltage over variations in junction temperature and input voltage A high quality low ESR ceramic bypass capacitor is required on the VBIAS pin X7R or X5R grade dielectrics are recommended because their values are more stable over temperature The bypass capacitor should be placed close to the VBIAS pin and returned to AGND External loading on VBIAS is allowed with the caution that...

Page 14: ...wing in both N channel power MOSFETs during the switching transitions by actively controlling the turnon times of the MOSFET drivers The high side driver does not turn on until the voltage at the gate of the low side FET is below 2 V While the low side driver does not turn on until the voltage at the gate of the high side MOSFET is below 2 V The high side and low side drivers are designed with 300...

Page 15: ...erials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as def...

Page 16: ...e Package Type Package Drawing Pins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant TPS54810PWPR HTSSOP PWP 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 PACKAGE MATERIALS INFORMATION www ti com 2 Jul 2009 Pack Materials Page 1 ...

Page 17: ...ions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TPS54810PWPR HTSSOP PWP 28 2000 346 0 346 0 33 0 PACKAGE MATERIALS INFORMATION www ti com 2 Jul 2009 Pack Materials Page 2 ...

Page 18: ......

Page 19: ......

Page 20: ......

Page 21: ...for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agre...

Reviews: