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4 TPS272C45EVM Schematic

J5

571-0500

J20

571-0500

J21

571-0500

J22

571-0100

EN1_IC

EN2_IC

4.7k

R4

4.7k

R11

4.7k

R12

4.7k

R10

4.7k

R7

DIA_EN_IC

SEL_IC

LATCH_IC

GND

OUT

1

DNC

2

P G

3

4

EN

5

NC

6

DELAY

7

IN

8

9

EP GND

TPS7A1633DGNR

U1

GND

1

3

D5
BAS21-7-F

1.0k

R8

1

2

J16

961102-6404-AR

1

2

3

J8

961103-6804-AR

1

2

3

J9

961103-6804-AR

1

2

3

J10

961103-6804-AR

1

2

3

J11

961103-6804-AR

1

2

3

J12

961103-6804-AR

1

2

3

J13

961103-6804-AR

GND_IC

1.00k

R16

4.7k

R15

100V
100pF

C8

SNS_IC

GND

SNS_BP

TP1

5010

TP2

5010

TP3

5010

TP4

5011

TP5

5011

J7

571-0100

VOUT1

VOUT2

1

2

3

J17

961103-6804-AR

BP_3V3

VDD_IC

SNS_BP

FLT_IC/FLT1_IC

EN2_IC

EN1_IC

GND

LATCH_IC

SEL_IC

BP_3V3

DIA_EN_BP

4.7k

R1

DIA_EN_IC

VS

VDD_IC

ILIMD_IC/FLT2_IC

1

2

J14

961102-6404-AR

1

2

J15

961102-6404-AR

ILIM1_IC

ILIM1_CTL_BP1

ILIM1_CTL_BP2

ILIM1_CTL_BP1
ILIM1_CTL_BP2

GND_IC

Analog Sensing

Current Limiting

BoosterPack Headers

3.3V LDO

Ground Network

Configuration Jumpers

GND_IC

22nF
100V

C3

GND

22nF
100V

C6

1.0k

R9

1

2

3

J18

961103-6804-AR

FLT_PU

BP_3V3

1

3

D1

BAS21-7-F

+3.3V

1

Analog_In

2

LP_UART_RX

3

LP_UART_TX

4

GP IO !

5

Analog In

6

S P I_CLK

7

GP IO !

8

I2C_SCL

9

I2C_SDA

10

+5V

21

GND

22

Analog_In

23

Analog_In

24

Analog_In

25

Analog_In

26

Analog_In/I2S_WS

27

Analog_In/I2S_SCLK

28

Analog_Out/I2S_SDout

29

Analog_Out/I2S_SDin

30

J1/J3

SSQ-110-03-T-D

GP IO !

31

GP IO !

32

GP IO !

33

GP IO !

34

Timer_Cap/GP IO !

35

Timer_Cap/GP IO !

36

P WM/GP IO !

37

P WM/GP IO !

38

P WM/GP IO !

39

P WM/GP IO !

40

GP IO !

11

S P I_CS /GP IO !

12

S P I_CS /GP IO !

13

S P I_MIS O

14

S P I_MOS I

15

RS T

16

GP IO

17

GP IO !

18

P WM/GP IO !

19

GND

20

J2/J4

SSQ-110-03-T-D

GND

1

2

3

Q1
2N7002Q-7-F

1

2

3

Q2
2N7002Q-7-F

FLT_PU

48.7

R6

5V

D6
SMAJ5.0CA

VDD

19

OUT1

1

OUT1

2

OUT1

3

OUT2

5

OUT2

6

OUT2

7

VS

8

VS

9

VS

23

VS

24

EN1

16

EN2

15

FLT

10

DIA_EN

12

ILIMD

18

LATCH

14

PowerPad

25

SEL

13

SNS

11

ILIM1

21

ILIM2

20

NC

4

NC

22

GND

17

TPS272C45A/D

U2

VDD_IC

GND

EN1_IC
EN2_IC

FLT_IC/FLT1_IC

DIA_EN_IC

SEL_IC

SNS_IC

LATCH_IC

ILIM1_IC

ILIM2_IC

48V

D2
SMCJ48A-TR

48V

D3
SMCJ48A-TR

GND

J6

571-0500

TP6

5011

GND

2.2

µ

F

50V

C1

3.3V

D7

MMSZ5226B-7-F

1

2

J19

961102-6404-AR

D9
STPS1150A

D8
STPS1150A

GND

TP10
5126

TP7

5126

4.7nF
100V

C4

100nF
100V

C5

100V
2.2uF

C7

100V
1uF

C2

TP8
5126

TP9
5126

TP11

5011

0

R5

0

R3

4.99k

R14

10.0k

R13

36V

D4
SMBJ36A-13-F

10k

R17

10k

R18

1

2

3

J23

961103-6804-AR

Configuration for Ver D

ILIMD_IC

ILIMD_IC/FLT2_IC

ILIMD_IC

FLT2_IC

4.7k

R20

1.0k

R19

FLT_PU

FLT2_IC

TP12
5126

19.6k

R2

Figure 4-1. TPS272C45EVM Schematic Drawing

www.ti.com

TPS272C45EVM Schematic

SLVUBV4A – DECEMBER 2020 – REVISED DECEMBER 2021

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TPS272C45 Evaluation Module

5

Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for TPS272C45

Page 1: ...tion 2 2 Compatibility Across Silicon Versions 3 3 BoosterPack Operation 4 4 TPS272C45EVM Schematic 5 5 Connection Descriptions 6 6 TPS272C45EVM Assembly Drawings and Layout 7 7 Current Limit Configur...

Page 2: ...ing the user to easily connect the TPS272C45 high side switch to an underlying microcontroller and write software to control and configure the device Features of the TPS272C45EVM include Multiplexed c...

Page 3: ...filter any transients above 5 V When using the C version of the device populate D2 D3 D8 and D9 with the relevant diodes required for inductive loading TI recommends the SMC series of diodes due to th...

Page 4: ...the pin To power the attached LaunchPad from the on board LDO of the TPS272C45EVM connect the jumper J19 Note that this feeds the output of the 3 3 V LDO on the TPS272C45EVM into the 3 3 V rail on the...

Page 5: ...alog_In I2S_WS 27 Analog_In I2S_SCLK 28 Analog_Out I2S_SDout 29 Analog_Out I2S_SDin 30 J1 J3 SSQ 110 03 T D GPIO 31 GPIO 32 GPIO 33 GPIO 34 Timer_Cap GPIO 35 Timer_Cap GPIO 36 PWM GPIO 37 PWM GPIO 38...

Page 6: ...he functionality of the device during fault conditions via the LATCH pin J13 Enables disables the on board 3 3 V LDO Must be set to top position marked on silk screen as 3 3 V LDO to allow J8 to J12 t...

Page 7: ...gure 6 1 3D Representation Figure 6 2 Top Layer www ti com TPS272C45EVM Assembly Drawings and Layout SLVUBV4A DECEMBER 2020 REVISED DECEMBER 2021 Submit Document Feedback TPS272C45 Evaluation Module 7...

Page 8: ...Figure 6 4 Ground Layer TPS272C45EVM Assembly Drawings and Layout www ti com 8 TPS272C45 Evaluation Module SLVUBV4A DECEMBER 2020 REVISED DECEMBER 2021 Submit Document Feedback Copyright 2021 Texas In...

Page 9: ...Bottom Layer www ti com TPS272C45EVM Assembly Drawings and Layout SLVUBV4A DECEMBER 2020 REVISED DECEMBER 2021 Submit Document Feedback TPS272C45 Evaluation Module 9 Copyright 2021 Texas Instruments I...

Page 10: ...its can be selected from an external microcontroller through the BoosterPack headers This feature can seen below in Figure 7 1 Figure 7 1 Multiplexed Current Limit With this configuration the user can...

Page 11: ...pin it can required to populate a Zener diode on pin D7 to regulate the maximum voltage going into the microcontroller s analog input By default a 1 k resistor is used as the SNS resistor R15 however...

Page 12: ...transient protection features Input TVS diode on VS D4 to protect against upstream power events populated Optional external inductive load turn off diode footprints on D2 D3 D8 and D9 to provide a mec...

Page 13: ...B SMBJ36A 13 F Diodes Inc J1 J3 J2 J4 Receptacle 2 54mm 10x2 Tin TH 10x2 Receptacle SSQ 110 03 T D Samtec J5 J6 J20 J21 Standard Banana Jack insulated 10A red 571 0500 571 0500 DEM Manufacturing J7 J2...

Page 14: ...t 5011 Keystone TP7 TP8 TP9 TP10 TP12 Test Point Multipurpose Green TH Green Multipurpose Testpoint 5126 Keystone U1 Single Output LDO 100 mA Fixed 3 3 V Output 3 to 60 V Input with Enable and Power G...

Page 15: ...ision December 2020 to Revision A December 2021 Page Added support for TPS272C45 version D 1 Updated Figure 4 1 5 Updated Figure 6 1 through Figure 6 5 7 www ti com Revision History SLVUBV4A DECEMBER...

Page 16: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 17: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 18: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 19: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 20: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 21: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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