Operation
3.1.1
DRVn and DONE Operation
To simultaneously observe the timing of the DRVn pulse along with the DONE signal, use a two channel
scope to probe the DRV_N and the DONE pins. Ensure that the MODE_SW is in the TIMER position.
Immediately after a rising edge of the DRV_N signal, press and release the DONE switch on the board.
When the DONE signal is asserted, the DRVn pulse should de-assert.
Figure 4. DONE and DRVn Signal Behavior in Timer Mode
3.1.2
DRVn and Boost Converter Output
To simultaneously observe the timing of the DRVn pulse along with the output of the boost converter, use
a two channel scope to probe the DRV_N and the VDD_UC pins. Immediately after a rising edge of the
DRV_N signal, the output of the boost converter should turn on, with a delay of approximately 2.5 ms to 5
ms. The output level should be approximately 3.3V.
Figure 5. Boost Converter Input (DRVn) and Output (VDD)
7
SNAU183 – July 2015
TPL5111EVM User 's Guide
Copyright © 2015, Texas Instruments Incorporated
