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J.A.G Aug 2006
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State Notes:
2
4
5
3
1
IDLE
Notes:
1. In SCI synchronous mode, this transition always occurs
approximately 3 ms after leaving Idle state. The diagnostics
byte transmission should have completed.
2. A falling edge on TxCT interrupts the Receive phase after
a delay of 0.9 ms. TxCT must remain low for at least 128
µs. If TxCT is still low after the 0.9 ms delay, the IC will go
to Idle mode and then directly to the diagnostics phase
1 clock cycle later ( Dotted line )
3. This transition only occurs in case above.
4. A falling edge on TxCT interrupts the Sleep state. Only
default mode is fully supported when starting an operation
from Sleep with only one falling edge on TxCT (because of
the 2 ms delay). For proper TxCT programming, TxCT has
to return to high and remain high during this delay
5. Idle mode is the next state in the case an undefined state.
(failsafe state machine)
3
1
2
3
2
4
5
