Texas Instruments TMS3705A Technical Training Manual Download Page 24 | Manualshive

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24

J.A.G Aug 2006

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Timing Diagram:

R/O mode

z

With write to MCR

NOTE:

For correct writing to the MCR, it is essential to know if the IC is in IDLE or SLEEP mode

PHASE

M.C.W. CHARGE RESPONSE

Init. Transmission

t

init

t

R

TxCT

t

diags

t

ch

D

S

D

= Diagnosis Byte,

S

= Start Byte

Data Bytes

SCIO

t

wake

~50µs

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Summary of Contents for TMS3705A

Page 1: ...J A G Aug 2006 LF Technical Training TMS3705A Transceiver IC ...

Page 2: ...al demodulator z Diagnosis function z Several operating modes self adapting or fixed frequency charge up automatic or fixed demodulator threshold asynchronous or synchronous data to µP z Reduced additional component count z PLL for internal clock generation z 2 4 MHz crystal or low cost ceramic resonator can be used 16 Pin SO Package Main Features 9 35 mm 6 12 mm ...

Page 3: ...3 J A G Aug 2006 A Transceiver Module with antenna ...

Page 4: ...FSEL 16 TXCT I O O O O I O I I O I I I O I I Input of RF amplifier Output of RF amplifier Test output for digital signals Test output for analog signals Antenna output 1 Ground for full bridge drivers Antenna output 2 Voltage supply for full bridge drivers Voltage supply for non power blocks Oscillator output Oscillator input Ground for non power blocks Ground for PLL Data output to microprocessor...

Page 5: ...NT1 ANT2 VDDA VSSA Control Logic with Mode Control Register Pre drivers Full Bridge RFAmplifier SFB SENSE Diagnosis Power on reset Controlled Frequency Divider VDD VSS OSC1 OSC2 TXCT F_SEL SCIO PLL D_TST A_TST VSSB 10k Digital Demodulator Tag Resonant Freq Measurement ...

Page 6: ... Aug 2006 Generic Circuit Diagram SENSE SFB D_TST A_TST ANT1 VSSA ANT2 VDDA TXCT F_SEL SCIO VSSB VSS OSC1 OSC2 VDD L1 C1 R1 R2 C2 C1 C4 Q1 4 MHz 1 16 8 9 TXCT input SCIO output Supply Voltage Ground U1 ANTENNA ...

Page 7: ...6 7 8 16 15 14 13 12 11 10 9 VDD VDDA VDD z Connect the blocking capacitors as close as possible to the supply pins z Tantalum capacitors are recommended z To prevent uncontrolled radiation it is recommended to connect the supply voltage symmetrically to VDDA and VDD ...

Page 8: ...eramic Oscillator is to be used one with an internal load capacitance of around 56 pF is recommended z An external oscillator signal can be fed into OSC1 OSC2 has to be left open a decoupling capacitor is recommended OSC1 OSC2 F_SEL PLL VSSB ...

Page 9: ...low bit frequency by the shift values and not by the absolute values z The threshold between the high bit and the low bit is defined as 6 5 kHz lower than that measured for the low bit frequency z After the charge phase the transponder response frequency is measured to determine the counter state for the low bit and high bit threshold VDD SCIO Digital Demodulator Transponder Resonance Frequency Me...

Page 10: ...0 µs will start to measure the low bit frequency of the 16 tag pre bits 100 µs 1 6 ms 1 7 ms TXCT SCIO Start Bit Frequency measuring starts Pre bits Begins looking for start byte 0x7E 0x7F z When TXCT goes high the module enters the read phase z 1 7 ms after TXCT goes high the IC starts looking for a valid start byte ...

Page 11: ...te is sent 2 ms after the start of the charge phase If normal antenna operation is detected then 0xAF is sent If no antenna oscillation is detected or a short detection occurs then 0xFF is sent Diagnostics Byte SFB SENSE Diagnosis A_TST 10k ...

Page 12: ...2006 z The OP Amp has a fixed internal voltage reference z A voltage gain of 5 is controlled by external resistance RX Amplifier R2 150k G 3 19 R1 47k Band Pass Limiter Vref RFAmplifier SFB SENSE Diagnosis A_TST 10k ...

Page 13: ...rnal components required for filtering and amplification z The analog sine wave is converted to a digital signal z High gain at least 1000 Band Pass Filter Limiter Band Pass Limiter Vref RFAmplifier SFB SENSE Diagnosis A_TST 10k ...

Page 14: ...rst z In Synchronous Mode a high state at the SCSI output indicates that a new byte is ready to be transmitted z The transmission rate is 15625 baud in asynchronous mode with 1 start byte high and 1 stop byte low SCI Encoder for Data Transmission to the Controller SCIO VDD Digital Demodulator Transponder Resonance Frequency Measurement SCI Encoder ...

Page 15: ...verted compared with the data from a transponder Typical transponder values R O Transponder 0x81 0x7E inverted R W Transponder 0x01 0xFE inverted DST Transponder 0x81 0x7E inverted SCI Encoder for Data Transmission to the Controller 2 SCIO VDD Digital Demodulator Transponder Resonance Frequency Measurement SCI Encoder ...

Page 16: ...16 J A G Aug 2006 SCIO Asynchronous Transmission z Timing diagram SCIO Start Bit Stop Bit tsci tsci LSB 1 2 3 4 5 6 MSB ...

Page 17: ...17 J A G Aug 2006 SCIO Synchronous Transmission z Timing diagram SCIO tsync tready LSB 1 2 3 4 5 6 MSB tsyn c TxCT Byte ready Stop bit tL_sync tt_sync µP Reads data Shift data ...

Page 18: ...c bit in the Mode Control Register MCR z The micro controller has to clock out the data bytes by sending 8 clock signals to the TXCT input z A high state on the SCIO indicates that a new byte is ready to be transmitted z The advantage of synchronous transmission Higher speed of the byte transmission Minimum clock period of 4µs x 8 5 34 µs per byte ...

Page 19: ...r on Reset VDD TXCT SCIO D_TST Digital Demodulator Transponder Resonance Frequency Measurement SCI Encoder z By writing to the MCR the mode of operation of the IC can be changed z The options include Asynchronous Synchronous data Frequency changing Demodulator threshold adjustment Test Mode ...

Page 20: ...J A G Aug 2006 Timing Diagram z Mode Control Register Write Protocol PHASE Low Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 CHARGE Start bit Test bit Init Transmission End of transmission tinit tmcr tmcr TxCT ...

Page 21: ...Bit 0 Start Bit 0 Start bit is always LOW Bit 1 Frequency selection Threshold adjust Bit 2 Frequency selection Threshold adjust Bit 3 Frequency selection Threshold adjust Bit 4 Frequency selection Threshold adjust Bit 5 SCI_Sync 0 default Asynchronous data transmission 1 Synchronous data transmission Bit 6 RX_AFC 0 default Automatic demodulator threshold adjustment 1 Demodulator threshold defined ...

Page 22: ... 0 0 116 Division factor selected by µC 0 0 1 0 117 Division factor selected by µC 1 0 1 0 118 Division factor selected by µC 0 1 1 0 119 Division factor selected by µC 1 1 1 0 120 Division factor selected by µC 0 0 0 1 121 Division factor selected by µC 1 0 0 1 122 Division factor selected by µC 0 1 0 1 123 Division factor selected by µC 1 1 0 1 124 Division factor selected by µC 1 1 1 1 Auto Div...

Page 23: ...23 J A G Aug 2006 Timing Diagram Default mode z Write to MCR PHASE M C W CHARGE RESPONSE Init Transmission tinit tR TxCT tdiags tch D S D Diagnosis Byte S Start Byte Data Bytes SCIO ...

Page 24: ... With write to MCR NOTE For correct writing to the MCR it is essential to know if the IC is in IDLE or SLEEP mode PHASE M C W CHARGE RESPONSE Init Transmission tinit tR TxCT tdiags tch D S D Diagnosis Byte S Start Byte Data Bytes SCIO twake 50µs ...

Page 25: ...te to MCR NOTE For correct writing to the MCR it is essential to know if the IC is in IDLE or SLEEP mode PHASE M C W CHARGE WRITE PROG RESPONSE Init Transmission tinit tR TxCT tdiags tch D S D Diagnosis Byte S Start Byte Data Bytes SCIO twake 50µs tprog ...

Page 26: ...rox 2 ms after leaving Idle state CHARGE Phase Charge phase continues 4 5 3 1 0 9 ms after TxCT goes low or 4ms after the start of Receive phase if no start bit is detected or otherwise 20 ms after start of Receive phase MCR bits received Diagnostics Byte sent TxCT GOES HIGH WRITE Phase Start of Write phase Frequency measurement Program phase TxCT REMAINS HIGH for 1 6 ms RECEIVE Phase Frequency me...

Page 27: ...w after the 0 9 ms delay the IC will go to Idle mode and then directly to the diagnostics phase 1 clock cycle later Dotted line 3 This transition only occurs in case above 4 A falling edge on TxCT interrupts the Sleep state Only default mode is fully supported when starting an operation from Sleep with only one falling edge on TxCT because of the 2 ms delay For proper TxCT programming TxCT has to ...

Page 28: ...11 07 26 001 Oct 1999 z DST Reference Manual 11 09 21 029 Dec 1998 z DST Sequence Control Specification 24 06 05 005 Jun 1996 z DSP Algorithm SW Requirements 24 09 05 012 Oct 1995 z Immobiliser Systems Design Guide Rev 01 Jan 1996 z Tricks and Hints for System Evaluation Ver 2 0 Sept 1999 ...

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