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5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR)
SRIO Registers
The bits in this register indicate any active interrupt requests from RX buffer descriptor queues. The RX
CPPI interrupt status register (RX_CPPI_ICSR) is shown in
Figure 79
and described in
Table 69
. For
additional programming information, see
Section 4.3.2
.
Figure 79. RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) - Address Offset 0240h
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS15
ICS14
ICS13
ICS12
ICS11
ICS10
ICS9
ICS8
ICS7
ICS6
ICS5
ICS4
ICS3
ICS2
ICS1
ICS0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 69. RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) Field Descriptions
Bit
Field
Value
Description
31–16
Reserved
0
These read-only bits return 0 when read.
15–0
ICSx
RX CPPI interrupt status
(x = 15 to 0)
0
RX buffer descriptor queue x has not generated an interrupt request.
1
RX buffer descriptor queue x has generated an interrupt request.
Serial RapidIO (SRIO)
134
SPRUE13A – September 2006
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