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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015

SPRS230N – OCTOBER 2003 – REVISED MAY 2012

www.ti.com

Table 6-25

shows the high-resolution PWM switching characteristics.

Table 6-25. High-Resolution PWM Characteristics at SYSCLKOUT = 60–100 MHz

MIN

TYP

MAX

UNIT

Micro Edge Positioning (MEP) step size

(1)

150

310

ps

(1)

Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.

Table 6-26

shows the eCAP timing requirement and

Table 6-27

shows the eCAP switching characteristics.

Table 6-26. Enhanced Capture (eCAP) Timing Requirement

(1)

TEST CONDITIONS

MIN

MAX

UNIT

t

w(CAP)

Capture input pulse width

Asynchronous

2t

c(SCO)

cycles

Synchronous

2t

c(SCO)

With input qualifier

1t

c(SCO)

+ t

w(IQSW)

(1)

For an explanation of the input qualifier parameters, see

Table 6-15

.

Table 6-27. eCAP Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

t

w(APWM)

Pulse duration, APWMx output high/low

20

ns

Table 6-28

shows the eQEP timing requirement and

Table 6-29

shows the eQEP switching

characteristics.

Table 6-28. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements

(1)

TEST CONDITIONS

MIN

MAX

UNIT

t

w(QEPP)

QEP input period

Asynchronous

(2)

/synchronous

2t

c(SCO)

cycles

With input qualifier

2[1t

c(SCO)

+ t

w(IQSW)

]

t

w(INDEXH)

QEP Index Input High time

Asynchronous

(2)

/synchronous

2t

c(SCO)

cycles

With input qualifier

2t

c(SCO)

+t

w(IQSW)

t

w(INDEXL)

QEP Index Input Low time

Asynchronous

(2)

/synchronous

2t

c(SCO)

cycles

With input qualifier

2t

c(SCO)

+ t

w(IQSW)

t

w(STROBH)

QEP Strobe High time

Asynchronous

(2)

/synchronous

2t

c(SCO)

cycles

With input qualifier

2t

c(SCO)

+ t

w(IQSW)

t

w(STROBL)

QEP Strobe Input Low time

Asynchronous

(2)

/synchronous

2t

c(SCO)

cycles

With input qualifier

2t

c(SCO)

+t

w(IQSW)

(1)

For an explanation of the input qualifier parameters, see

Table 6-15

.

(2)

Refer to the TMS320F280x, TMS320C280x, and TMS320F2801x DSC Silicon Errata (literature number

SPRZ171

) for limitations in the

asynchronous mode.

Table 6-29. eQEP Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

t

d(CNTR)xin

Delay time, external clock to counter increment

4t

c(SCO)

cycles

t

d(PCS-OUT)QEP

Delay time, QEP input edge to position compare sync output

6t

c(SCO)

cycles

116

Electrical Specifications

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Summary of Contents for TMS320F2801 Data

Page 1: ... Signal Processors Data Manual PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Literature Number SPRS230N October 2003 Revised May 2012 ...

Page 2: ... Low Power Modes 37 3 2 17 Peripheral Frames 0 1 2 PFn 38 3 2 18 General Purpose Input Output GPIO Multiplexer 38 3 2 19 32 Bit CPU Timers 0 1 2 38 3 2 20 Control Peripherals 38 3 2 21 Serial Port Peripherals 39 3 3 Register Map 39 3 4 Device Emulation Registers 41 3 5 Interrupts 41 3 5 1 External Interrupts 44 3 6 System Control 45 3 6 1 OSC and PLL Block 46 3 6 1 1 External Reference Oscillator ...

Page 3: ...ck Requirements and Characteristics 105 6 8 Power Sequencing 106 6 8 1 Power Management and Supervisory Circuit Solutions 106 6 9 General Purpose Input Output GPIO 109 6 9 1 GPIO Output Timing 109 6 9 2 GPIO Input Timing 110 6 9 3 Sampling Window Width for Input Signals 111 6 9 4 Low Power Mode Wakeup Timing 112 6 10 Enhanced Control Peripherals 115 6 10 1 Enhanced Pulse Width Modulator ePWM Timin...

Page 4: ...g Module 50 4 1 CPU Timers 52 4 2 CPU Timer Interrupt Signals and Output Signal 53 4 3 Multiple PWM Modules in a 280x System 54 4 4 ePWM Sub Modules Showing Critical Internal Signal Interconnections 56 4 5 eCAP Functional Block Diagram 58 4 6 eQEP Functional Block Diagram 60 4 7 Block Diagram of the ADC Module 63 4 8 ADC Pin Connections With Internal Reference 64 4 9 ADC Pin Connections With Exter...

Page 5: ...am 113 6 16 HALT Wake Up Using GPIOn 114 6 17 PWM Hi Z Characteristics 115 6 18 ADCSOCAO or ADCSOCBO Timing 117 6 19 External Interrupt Timing 117 6 20 SPI Master Mode External Timing Clock Phase 0 120 6 21 SPI Master Mode External Timing Clock Phase 1 122 6 22 SPI Slave Mode External Timing Clock Phase 0 124 6 23 SPI Slave Mode External Timing Clock Phase 1 125 6 24 ADC Power Up Control Bit Timin...

Page 6: ... Configuration and Control Registers 53 4 2 ePWM Control and Status Registers 55 4 3 eCAP Control and Status Registers 59 4 4 eQEP Control and Status Registers 61 4 5 ADC Registers 66 4 6 3 3 V eCAN Transceivers 68 4 7 CAN Register Map 71 4 8 SCI A Registers 73 4 9 SCI B Registers 73 4 10 SPI A Registers 76 4 11 SPI B Registers 76 4 12 SPI C Registers 77 4 13 SPI D Registers 77 4 14 I2C A Register...

Page 7: ...Switching Characteristics 117 6 31 External Interrupt Timing Requirements 117 6 32 External Interrupt Switching Characteristics 117 6 33 I2C Timing 118 6 34 SPI Master Mode External Timing Clock Phase 0 119 6 35 SPI Master Mode External Timing Clock Phase 1 121 6 36 SPI Slave Mode External Timing Clock Phase 0 123 6 37 SPI Slave Mode External Timing Clock Phase 1 124 6 38 ADC Electrical Characteri...

Page 8: ...C2802 32K x 16 ROM 6K x 16 SARAM 80 ns 12 5 MSPS F2809 only C2801 16K x 16 ROM 6K x 16 SARAM 160 ns 6 25 MSPS 280x Boot ROM 4K x 16 267 ns 3 75 MSPS F2801x With Software Boot Modes via SCI SPI Internal or External Reference CAN I2C and Parallel I O Up to 35 Individually Programmable Standard Math Tables Multiplexed GPIO Pins With Input Filtering Clock and System Control Advanced Emulation Features...

Page 9: ...oftware To simplify programming for C28x devices it is recommended that users download and use the C C Header Files and Example s to begin developing software for the C28x devices and their various peripherals After downloading the appropriate header file package for your device refer to the following resources for step by step instructions on how to run the peripheral examples and use the header ...

Page 10: ...anding control applications Throughout this document TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28015 and TMS320F28016 are abbreviated as F2809 F2808 F2806 F2802 F2801 C2802 C2801 F28015 and F28016 respectively TMS320F28015 and TMS320F28016 are abbreviated as F2801x Table 2 1 provides a summary of features for each device 10 Introduction Copyright 20...

Page 11: ...I 0 SPI A B C D SPI A B C D SPI A B C D SPI A B SPI A B SPI A B SPI A B Serial Communications Interface SCI 0 SCI A B SCI A B SCI A B SCI A SCI A SCI A SCI A Enhanced Controller Area Network eCAN 0 eCAN A B eCAN A B eCAN A eCAN A eCAN A eCAN A eCAN A Inter Integrated Circuit I2C 0 I2C A I2C A I2C A I2C A I2C A I2C A I2C A Digital I O pins shared 35 35 35 35 35 35 35 External interrupts 3 3 3 3 3 3...

Page 12: ...rial Communications Interface SCI 0 SCI A SCI A SCI A SCI A Enhanced Controller Area Network eCAN 0 eCAN A eCAN A eCAN A Inter Integrated Circuit I2C 0 I2C A I2C A I2C A I2C A Digital I O pins shared 35 35 35 35 External interrupts 3 3 3 3 1 8 V Core 1 8 V Core 1 8 V Core 1 8 V Core Supply voltage 3 3 V I O 3 3 V I O 3 3 V I O 3 3 V I O 100 Pin PZ Yes Yes Yes Yes Packaging 100 Ball GGM ZGM Yes Yes...

Page 13: ... GPIO21 EQEP1B SPISOMIC CANRXB V SS V SS V SS V SS V SS V SS1AGND V SSA2 V SSAIO V DD V DDA2 V DD1A18 V DDIO V DD V DD V DDIO GPIO11 EPWM6B SCIRXDB ECAP4 GPIO22 EQEP1S SPICLKC SCITXDB TMS TDI GPIO23 EQEP1I SPISTEC SCIRXDB ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB7 ADCINB6 ADCINB5 ADCINB4 ADCREFIN ADCREFM ADCREFP ADCRESEXT GPIO34 GPIO1 EPWM1B SPISIMOD GPIO2 EPWM2A GPIO3 EPWM2B SPISOMID GPIO16 SPISIMOA...

Page 14: ...XDB GPIO6 EPWM4A EPWMSYNCI EPWMSYNCO GPIO19 SPISTEA SCIRXDB GPIO7 EPWM4B SPISTED ECAP2 GPIO9 EPWM5B SCITXDB ECAP3 GPIO20 EQEP1A SPISIMOC GPIO10 EPWM6A ADCSOCBO GPIO8 EPWM5A ADCSOCAO XCLKOUT GPIO21 EQEP1B SPISOMIC V SS V SS V SS V SS V SS V SS1AGND V SSA2 V SSAIO V DD V DDA2 V DD1A18 V DDIO V DD V DD V DDIO GPIO11 EPWM6B SCIRXDB ECAP4 GPIO22 EQEP1S SPICLKC SCITXDB TMS TDI GPIO23 EQEP1I SPISTEC SCIR...

Page 15: ...LKA GPIO6 EPWMSYNCI EPWMSYNCO GPIO19 SPISTEA GPIO7 ECAP2 GPIO9 GPIO20 EQEP1A GPIO10 ADCSOCBO GPIO8 ADCSOCAO XCLKOUT GPIO21 EQEP1B V SS V SS V SS V SS V SS V SS1AGND V SSA2 V SSAIO V DD V DDA2 V DD1A18 V DDIO V DD V DD V DDIO GPIO11 GPIO22 EQEP1S TMS TDI GPIO23 EQEP1I ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB7 ADCINB6 ADCINB5 ADCINB4 ADCREFIN ADCREFM ADCREFP ADCRESEXT GPIO34 GPIO1 EPWM1B GPIO2 EPWM2A ...

Page 16: ...NCI EPWMSYNCO GPIO19 SPISTEA GPIO7 EPWM4B ECAP2 GPIO9 GPIO20 GPIO10 ADCSOCBO GPIO8 ADCSOCAO XCLKOUT GPIO21 V SS V SS V SS V SS V SS V SS1AGND V SSA2 V SSAIO V DD V DDA2 V DD1A18 V DDIO V DD V DD V DDIO GPIO11 GPIO22 TMS TDI GPIO23 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB7 ADCINB6 ADCINB5 ADCINB4 ADCREFIN ADCREFM ADCREFP ADCRESEXT GPIO34 GPIO1 EPWM1B GPIO2 EPWM2A GPIO3 EPWM2B GPIO16 SPISIMOA TZ5 GPIO...

Page 17: ...VSS ADCINB2 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0 ADCINB7 ADCINB1 ADCINB0 ADCLO ADCRESEXT ADCREFIN ADCREFP ADCREFM ADCINB3 ADCINB5 ADCINB4 ADCINB6 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230N OCTOBER 2003 REVISED MAY 2012 Figure 2 5 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS3...

Page 18: ...commended on this pin The value of this resistor should be based on the drive strength of the debugger pods applicable to the design A 2 2 kΩ to 4 7 kΩ resistor is generally adequate Since this is application specific it is recommended that each target board be validated for proper operation of the debugger and the application Emulator pin 1 When TRST is driven high this pin is used as an interrup...

Page 19: ... 16 F3 ADC Group A Channel 7 input I ADCINA6 17 F4 ADC Group A Channel 6 input I ADCINA5 18 G4 ADC Group A Channel 5 input I ADCINA4 19 G1 ADC Group A Channel 4 input I ADCINA3 20 G2 ADC Group A Channel 3 input I ADCINA2 21 G3 ADC Group A Channel 2 input I ADCINA1 22 H1 ADC Group A Channel 1 input I ADCINA0 23 H2 ADC Group A Channel 0 input I ADCINB7 34 K5 ADC Group B Channel 7 input I ADCINB6 33 ...

Page 20: ...PERIPHERAL SIGNALS 1 2 GPIO0 General purpose input output 0 I O Z 3 EPWM1A Enhanced PWM1 Output A and HRPWM channel O 47 K8 GPIO1 General purpose input output 1 I O Z 3 EPWM1B Enhanced PWM1 Output B O 44 K7 SPISIMOD SPI D slave in master out I O not available on 2801 2802 GPIO2 General purpose input output 2 I O Z 3 EPWM2A Enhanced PWM2 Output A and HRPWM channel O 45 J7 1 Some peripheral function...

Page 21: ...nput output 3 I O not available on 2801 2802 GPIO10 General purpose input output 10 I O Z 1 EPWM6A Enhanced PWM6 output A and HRPWM channel O not available on 2801 2802 64 E10 CANRXB Enhanced CAN B receive I not available on 2801 2802 F2806 ADCSOCBO ADC start of conversion B O GPIO11 General purpose input output 11 I O Z 1 EPWM6B Enhanced PWM6 output B O not available on 2801 2802 70 D9 SCIRXDB SC...

Page 22: ... 2802 GPIO23 General purpose input output 23 I O Z 1 EQEP1I Enhanced QEP1 index I O 72 C10 SPISTEC SPI C slave transmit enable I O not available on 2801 2802 SCIRXDB SCI B receive I not available on 2801 2802 GPIO24 General purpose input output 24 I O Z 1 ECAP1 Enhanced capture 1 I O 83 C7 EQEP2A Enhanced QEP2 input A I not available on 2801 2802 SPISIMOB SPI B slave in master out I O GPIO25 Gener...

Page 23: ...I2C data open drain bidirectional port I OD 100 A1 EPWMSYNCI Enhanced PWM external sync pulse input I ADCSOCAO ADC start of conversion O GPIO33 General Purpose Input Output 33 I O Z 1 SCLA I2C clock open drain bidirectional port I OD 5 C1 EPWMSYNCO Enhanced PWM external synch pulse output O ADCSOCBO ADC start of conversion O GPIO34 General Purpose Input Output 34 I O Z 1 43 G7 1 The pullups on GPI...

Page 24: ...x 16 C2801 FLASH 128K x 16 F2809 64K x 16 F2808 32K x 16 F2806 32K x 16 F2802 16K x 16 F2801 16K x 16 F2801x OTP 1K x 16 D Protected by the code security module 32 bit CPU TIMER 0 32 bit CPU TIMER 1 32 bit CPU TIMER 2 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230N OCTOBER 2003 REVISED MAY 2012 www ti com 3 Functional Overview ...

Page 25: ...3F0000 3FFFFF 24x 240x equivalent program space ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ PIE Vector RAM 256 x 16 Enabled if ENPIE 1 0x00 0E00 0x3F C000 Reserved Reserved Reserved Reserved Reserved M0 SARAM 1K y 16 0x00 0040 Reserved TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320...

Page 26: ...x 240x equivalent program space ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ PIE Vector RAM 256 x 16 Enabled if ENPIE 1 0x00 0E00 0x3F C000 M0 Vector RAM 32 x 32 Enabled if VMAP 0 0x00 0040 Reserved Reserved Reserved Reserved Reserved Reserved TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

Page 27: ...me 1 protected Peripheral Frame 2 protected ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ PIE Vector RAM 256 x 16 Enabled if ENPIE 1 Vectors 32 y 32 enabled if VMAP 1 ENPIE 0 0x00 0E00 Reserved Reserved Reserved Reserved Reserved Reserved M0 SARAM 1K y 16 M0 Vector RAM 32 x 32 Enabled if VMAP 0 0x00 0040 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 T...

Page 28: ...ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ PIE Vector RAM 256 x 16 Enabled if ENPIE 1 0x00 0E00 Reserved Reserved Reserved Reserved Reserved Reserved 0x00 0040 M0 Vector RAM 32 x 32 Enabled if VMAP 0 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230N OCTOBER 2003 REVISED MAY 2012 www ti com A The 1K x 16 OTP has been replaced with 1K x 1...

Page 29: ...ÉÉ ÉÉÉÉÉ ÉÉÉÉÉ PIE Vector RAM 256 x 16 Enabled if ENPIE 1 0x00 0E00 Reserved Reserved Reserved M0 SARAM 1K y 16 M0 Vector RAM 32 x 32 Enabled if VMAP 0 0x00 0040 Reserved Reserved Reserved TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230N OCTOBER 2003 REVISED MAY 2012 A The 1K x 16 OTP has been replaced with 1K x 16 RO...

Page 30: ... 0x3E BFFF Sector D 16K x 16 0x3E C000 0x3E FFFF Sector C 16K x 16 0x3F 0000 0x3F 3FFF Sector B 16K x 16 0x3F 4000 0x3F 7F7F Sector A 16K x 16 Program to 0x0000 when using the 0x3F 7F80 0x3F 7FF5 Code Security Module Boot to Flash Entry Point 0x3F 7FF6 0x3F 7FF7 program branch instruction here Security Password 128 Bit 0x3F 7FF8 0x3F 7FFF Do not program to all zeros Table 3 3 Addresses of Flash Se...

Page 31: ...s how to handle these memory locations Table 3 5 Impact of Using the Code Security Module FLASH ROM ADDRESS Code security enabled Code security disabled Code security enabled Code security disabled 0x3F 7F80 0x3F 7FEF Application code and data Fill with 0x0000 Application code and data Fill with 0x0000 0x3F 7FF0 0x3F 7FF5 Reserved for data only Reserved for TI Do not use 0x3D 7BFC 0x3D 7BFF Applic...

Page 32: ...ral Frame 2 Fixed 2 wait reads L0 and L1 SARAMs 0 wait Programmed via the Flash registers 1 wait state operation Programmable OTP is possible at a reduced CPU frequency See Section 3 2 5 1 wait minimum for more information Programmed via the Flash registers 0 wait state operation Programmable is possible at reduced CPU frequency The CSM password Flash 0 wait minimum locations are hardwired for 16 ...

Page 33: ...ory bus architecture contains a program read bus data read bus and data write bus The program read bus consists of 22 address lines and 32 data lines The data read and write busses consist of 32 address lines and 32 data lines each The 32 bit wide data busses enable single cycle 32 bit operations The multiple bus architecture commonly termed Harvard Bus enables the C28x to fetch an instruction rea...

Page 34: ...d to enable the flash module to achieve higher performance The flash OTP is mapped to both program and data space therefore it can be used to execute code or store data information Note that addresses 0x3F7FF0 0x3F7FF5 are reserved for data variables and should not contain program code NOTE The F2809 F2808 F2806 F2802 F2801 Flash and OTP wait states can be configured by the application This allows...

Page 35: ...ion or to select boot software that is programmed in the internal Flash ROM The Boot ROM also contains standard tables such as SIN COS waveforms for use in math related algorithms Table 3 7 Boot Mode Selection GPIO18 GPIO29 MODE DESCRIPTION SPICLKA GPIO34 SCITXDA SCITXDB Boot to Flash ROM Jump to Flash ROM address 0x3F 7FF6 1 1 1 You must have programmed a branch instruction here prior to reset to...

Page 36: ...E WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY EITHER ROM OR FLASH AND IS WARRANTED BY TEXAS INSTRUMENTS TI IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS TO CONFORM TO TI S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE TI DOES NOT HOWEVER WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN ...

Page 37: ...ip oscillator circuit A PLL is provided supporting up to 10 input clock scaling ratios The PLL ratios can be changed on the fly in software enabling the user to scale back on operating frequency if lower power operation is desired Refer to the Electrical Specification section for timing details The PLL block can be set in bypass mode 3 2 14 Watchdog The 280x devices contain a watchdog timer The us...

Page 38: ...cation cycles This is to filter unwanted noise glitches The GPIO signals can also be used to bring the device out of specific low power modes 3 2 19 32 Bit CPU Timers 0 1 2 CPU Timers 0 1 and 2 are identical 32 bit timers with presettable periods and with 16 bit clock prescaling The timers have a 32 bit count down register which generates an interrupt when the counter reaches zero The counter is d...

Page 39: ...vice communications are supported by the master slave operation of the SPI On the 280x the SPI contains a 16 level receive and transmit FIFO for reducing interrupt servicing overhead SCI The serial communications interface is a two wire asynchronous serial port commonly known as UART On the 280x the SCI contains a 16 level receive and transmit FIFO for reducing interrupt servicing overhead I2C The...

Page 40: ...sters 0x6000 0x60FF 256 bits in other eCAN control registers are EALLOW protected eCANA Mailbox RAM 0x6100 0x61FF 256 Not EALLOW protected Some eCAN control registers and selected eCANB Registers 0x6200 0x62FF 256 bits in other eCAN control registers are EALLOW protected eCANB Mailbox RAM 0x6300 0x63FF 256 Not EALLOW protected ePWM1 Registers 0x6800 0x683F 64 ePWM2 Registers 0x6840 0x687F 64 ePWM3...

Page 41: ...2808 0x00FE F2809 0x0014 F28016 0x001C F28015 0xFF2C C2801 0xFF24 C2802 REVID 0x0883 1 Revision ID Register 0x0000 Silicon Rev 0 TMX 0x0001 Silicon Rev A TMX 0x0002 Silicon Rev B TMS 0x0003 Silicon Rev C TMS Revision ID Register 0x0000 Silicon rev 0 TMS F2809 only PROTSTART 0x0884 1 Block Protection Start Address Register PROTRANGE 0x0885 1 Block Protection Range Address Register 1 The first byte ...

Page 42: ...0 nmi_select 1 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230N OCTOBER 2003 REVISED MAY 2012 www ti com When the PIE is enabled TRAP 1 through TRAP 12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group For example TRAP 1 fetches the vector from INT1 1 TRAP 2 fet...

Page 43: ... B SPI A SPI A INT7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A INT8 Reserved Reserved Reserved Reserved Reserved Reserved I2C A I2C A ECAN1_INTB ECAN0_INTB ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA INT9 CAN B CAN B CAN A CAN A SCI B SCI B SCI A SCI A INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT1...

Page 44: ...ster PIEIFR8 0x0CF1 1 PIE INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE INT12 Group Enable Register PIEIFR12 ...

Page 45: ...rrupt can be enabled disabled or qualified using positive negative or both positive and negative edge For more information see the TMS320x280x 2801x 2804x DSP System Control and Interrupts Reference Guide literature number SPRU712 3 6 System Control This section describes the 280x oscillator PLL and clocking mechanisms the watchdog function and the low power modes Figure 3 9 shows the various cloc...

Page 46: ... and Status Register WDCNTR 0x7023 1 Watchdog Counter Register Reserved 0x7024 1 Reserved WDKEY 0x7025 1 Watchdog Reset Key Register Reserved 0x7026 0x7028 3 Reserved WDCR 0x7029 1 Watchdog Control Register Reserved 0x702A 0x702F 6 Reserved 1 All of the registers in this table are EALLOW protected 3 6 1 OSC and PLL Block Figure 3 10 shows the OSC and PLL block on the 280x Figure 3 10 OSC and PLL B...

Page 47: ...tions for the external quartz crystal for a frequency of 20 MHz are listed below Fundamental mode parallel resonant CL load capacitance 12 pF CL1 CL2 24 pF Cshunt 6 pF ESR range 30 to 60 Ω TI recommends that customers have the resonator crystal vendor characterize the operation of their device with the DSP chip The resonator crystal vendor has the equipment and expertise to tune the tank circuit T...

Page 48: ... n 1001 OSCCLK 9 n 1010 OSCCLK 10 n 1011 1111 Reserved 1 This register is EALLOW protected 2 CLKIN is the input clock to the CPU SYSCLKOUT is the output clock from the CPU The frequency of SYSCLKOUT is the same as CLKIN If CLKINDIV 0 n 2 if CLKINDIV 1 n 1 NOTE PLLSTS CLKINDIV enables or bypasses the divide by two block before the clock is fed to the core This bit must be 0 before writing to the PL...

Page 49: ...d peripherals at a typical frequency of 1 5 MHz Limp mode is not specified to work from power up only after input clocks have been present initially In PLL bypass mode the limp mode clock from the PLL is automatically routed to the CPU if the input clock is removed or absent Normally when the input clocks are present the watchdog counter decrements to initiate a watchdog reset or WDINT interrupt H...

Page 50: ...ich will reset the watchdog counter Figure 3 14 shows the various functional blocks within the watchdog module A The WDRST signal is driven low for 512 OSCCLK cycles Figure 3 14 Watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE STANDBY mode In STANDBY mode all peripherals are turned off on the device The only peripheral that remains functional is the watchdog T...

Page 51: ...e 24x 240x the clock is turned off 3 On the C28x the JTAG port can still function even if the CPU clock CLKIN is turned off The various low power modes operate as follows IDLE Mode This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor The LPM block performs no tasks during this mode as long as the LPMCR0 LPM bits are set to 0 0 STANDBY Mode Any GPIO port A sig...

Page 52: ...Up to two enhanced controller area network eCAN modules eCAN A eCAN B Up to two serial communications interface modules SCI A SCI B Up to four serial peripheral interface SPI modules SPI A SPI B SPI C SPI D Inter integrated circuit module I2C Digital I O and shared pin functions 4 1 32 Bit CPU Timers 0 1 2 There are three 32 bit CPU timers on the 280x devices CPU TIMER0 1 2 CPU Timer 0 and CPU Tim...

Page 53: ... 2 Configuration and Control Registers NAME ADDRESS SIZE x16 DESCRIPTION TIMER0TIM 0x0C00 1 CPU Timer 0 Counter Register TIMER0TIMH 0x0C01 1 CPU Timer 0 Counter Register High TIMER0PRD 0x0C02 1 CPU Timer 0 Period Register TIMER0PRDH 0x0C03 1 CPU Timer 0 Period Register High TIMER0TCR 0x0C04 1 CPU Timer 0 Control Register Reserved 0x0C05 1 Reserved TIMER0TPR 0x0C06 1 CPU Timer 0 Prescale Register T...

Page 54: ...2TPR 0x0C16 1 CPU Timer 2 Prescale Register TIMER2TPRH 0x0C17 1 CPU Timer 2 Prescale Register High 0x0C18 Reserved 40 Reserved 0x0C3F 4 2 Enhanced PWM Modules ePWM1 2 3 4 5 6 The 280x device contains up to six enhanced PWM modules ePWM Figure 4 3 shows a block diagram of multiple ePWM modules Figure 4 4 shows the signal interconnections with the ePWM See the TMS320x280x 2801x 2804x Enhanced Pulse ...

Page 55: ...gister Set DBCTL 0x680F 0x684F 0x688F 0x68CF 0x690F 0x694F 1 1 Dead Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68D0 0x6910 0x6950 1 0 Dead Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 0x6911 0x6951 1 0 Dead Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 0x6912 0x6952 1 0 Trip Zone Select Register 1 TZCTL 0x6...

Page 56: ... Trip Zone TZ CTR ZERO EPWMxAO EPWMxBO EPWMxTZINT TZ1 to TZ6 HiRes PWM HRPWM CTR PRD CTR ZERO CTR CMPB CTR CMPA CTR_Dir Event Trigger and Interrupt ET EPWMxINT EPWMxSOCA EPWMxSOCB CTR ZERO TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230N OCTOBER 2003 REVISED MAY 2012 www ti com Figure 4 4 ePWM Sub Modules Showing Critical Intern...

Page 57: ...Compare A and Phase registers of the ePWM module HRPWM capabilities are offered only on the A signal path of an ePWM module that is on the EPWMxA output EPWMxB output has conventional PWM capabilities 4 4 Enhanced CAP Modules eCAP1 2 3 4 The 280x device contains up to four enhanced capture eCAP modules Figure 4 5 shows a functional block diagram of a module See the TMS320x280x 2801x 2804x Enhanced...

Page 58: ...lect CTR PRD CTR_OVF 4 PWM Compare Logic CTR 0 31 PRD 0 31 CMP 0 31 CTR CMP CTR PRD CTR_OVF OVF APWM Mode Delta Mode 4 Capture Events CEVT 1 4 APRD Shadow 32 32 32 32 32 CMP 0 31 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230N OCTOBER 2003 REVISED MAY 2012 www ti com Figure 4 5 eCAP Functional Block Diagram 58 Peripherals Copyr...

Page 59: ...egister Reserved 0x6A0C 0x6A2C 0x6A4C 0x6A6C 8 Reserved 0x6A12 0x6A32 0x6A52 0x6A72 ECCTL1 0x6A14 0x6A34 0x6A54 0x6A74 1 Capture Control Register 1 ECCTL2 0x6A15 0x6A35 0x6A55 0x6A75 1 Capture Control Register 2 ECEINT 0x6A16 0x6A36 0x6A56 0x6A76 1 Capture Interrupt Enable Register ECFLG 0x6A17 0x6A37 0x6A57 0x6A77 1 Capture Interrupt Flag Register ECCLR 0x6A18 0x6A38 0x6A58 0x6A78 1 Capture Inter...

Page 60: ... QCTMR QCPRD 16 16 QCAPCTL EQEPxENCLK SYSCLKOUT To CPU Data Bus TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230N OCTOBER 2003 REVISED MAY 2012 www ti com 4 5 Enhanced QEP Modules eQEP1 2 The 280x device contains up to two enhanced quadrature encoder eQEP modules See the TMS320x280x 2801x 2804x Enhanced Quadrature Encoder Pulse e...

Page 61: ...53 1 0 eQEP Watchdog Period Register QDECCTL 0x6B14 0x6B54 1 0 eQEP Decoder Control Register QEPCTL 0x6B15 0x6B55 1 0 eQEP Control Register QCAPCTL 0x6B16 0x6B56 1 0 eQEP Capture Control Register QPOSCTL 0x6B17 0x6B57 1 0 eQEP Position compare Control Register QEINT 0x6B18 0x6B58 1 0 eQEP Interrupt Enable Register QFLG 0x6B19 0x6B59 1 0 eQEP Interrupt Flag Register QCLR 0x6B1A 0x6B5A 1 0 eQEP Inte...

Page 62: ... EOS Sequencer can operate in start stop mode allowing multiple time sequenced triggers to synchronize conversions SOCA and SOCB triggers can operate independently in dual sequencer mode Sample and hold S H acquisition time window has separate prescale control The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals The ADC interface is built around a fast 12 ...

Page 63: ...isters are accessed at the SYSCLKOUT rate The internal timing of the ADC module is controlled by the high speed peripheral clock HSPCLK 2 The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows ADCENCLK On reset this signal will be low While reset is active low XRS the clock to the register will still function This is necessary to make sure all registers an...

Page 64: ...ound Pin ADC Analog Ground Pin 22 k 2 2 F μ A 2 2 F μ A TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230N OCTOBER 2003 REVISED MAY 2012 www ti com Figure 4 8 shows the ADC pin biasing for internal reference and Figure 4 9 shows the ADC pin biasing for external reference A TAIYO YUDEN LMK212BJ225MG T or equivalent B External decou...

Page 65: ...eference Select register depending on the voltage used on this pin TI recommends TI part REF3020 or equivalent for 2 048 V generation Overall gain accuracy will be determined by accuracy of this voltage source Figure 4 9 ADC Pin Connections With External Reference NOTE The temperature rating of any recommended component must match the rating of the end product 4 6 1 ADC Connections if the ADC Is N...

Page 66: ...LT7 0x710F 0x0B07 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x7110 0x0B08 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x7111 0x0B09 1 ADC Conversion Result Buffer Register 9 ADCRESULT10 0x7112 0x0B0A 1 ADC Conversion Result Buffer Register 10 ADCRESULT11 0x7113 0x0B0B 1 ADC Conversion Result Buffer Register 11 ADCRESULT12 0x7114 0x0B0C 1 ADC Conversion Result Buffer Register 12...

Page 67: ...programmable interrupt scheme with two interrupt levels Employs a programmable alarm on transmission or reception time out Low power mode Programmable wake up on bus activity Automatic reply to a remote request message Automatic retransmission of a frame in case of loss of arbitration or error 32 bit local network time counter synchronized by a specific message communication in conjunction with ma...

Page 68: ...4 6 3 3 V eCAN Transceivers SUPPLY LOW POWER SLOPE PART NUMBER VREF OTHER TA VOLTAGE MODE CONTROL SN65HVD230 3 3 V Standby Adjustable Yes 40 C to 85 C SN65HVD230Q 3 3 V Standby Adjustable Yes 40 C to 125 C SN65HVD231 3 3 V Sleep Adjustable Yes 40 C to 85 C SN65HVD231Q 3 3 V Sleep Adjustable Yes 40 C to 125 C SN65HVD232 3 3 V None None None 40 C to 85 C SN65HVD232Q 3 3 V None None None 40 C to 125 ...

Page 69: ...Control and Status Registers 6000h 603Fh Local Acceptance Masks LAM 32 x 32 Bit RAM 6040h 607Fh 6080h 60BFh 60C0h 60FFh eCAN A Memory 512 Bytes Message Object Time Stamps MOTS 32 x 32 Bit RAM Message Object Time Out MOTO 32 x 32 Bit RAM Mailbox 0 6100h 6107h Mailbox 1 6108h 610Fh Mailbox 2 6110h 6117h Mailbox 3 6118h 611Fh eCAN A Memory RAM 512 Bytes Mailbox 4 6120h 6127h Mailbox 28 61E0h 61E7h Ma...

Page 70: ...Message Control MSGCTRL Message Data Low MDL Message Data High MDH Message Mailbox 16 Bytes Control and Status Registers 6200h 623Fh Local Acceptance Masks LAM 32 x 32 Bit RAM 6240h 627Fh 6280h 62BFh 62C0h 62FFh eCAN B Memory 512 Bytes Message Object Time Stamps MOTS 32 x 32 Bit RAM Message Object Time Out MOTO 32 x 32 Bit RAM Mailbox 0 6300h 6307h Mailbox 1 6308h 630Fh Mailbox 2 6310h 6317h Mailb...

Page 71: ...1 Remote frame pending CANGAM 0x6012 0x6212 1 Global acceptance mask CANMC 0x6014 0x6214 1 Master control CANBTC 0x6016 0x6216 1 Bit timing configuration CANES 0x6018 0x6218 1 Error and status CANTEC 0x601A 0x621A 1 Transmit error counter CANREC 0x601C 0x621C 1 Receive error counter CANGIF0 0x601E 0x621E 1 Global interrupt flag 0 CANGIM 0x6020 0x6220 1 Global interrupt mask CANGIF1 0x6022 0x6222 1...

Page 72: ...rmat One start bit Data word length programmable from one to eight bits Optional even odd no parity bit One or two stop bits Four error detection flags parity overrun framing and break detection Two wake up multiprocessor modes idle line and address bit Half or full duplex operation Double buffered receive and transmit functions Transmitter and receiver operations can be accomplished through inter...

Page 73: ...eripheral Frame 2 space This space only allows 16 bit accesses 32 bit accesses produce undefined results 2 These registers are new registers for the FIFO mode Table 4 9 SCI B Registers 1 2 NAME ADDRESS SIZE x16 DESCRIPTION SCICCRB 0x7750 1 SCI B Communications Control Register SCICTL1B 0x7751 1 SCI B Control Register 1 SCIHBAUDB 0x7752 1 SCI B Baud Register High Bits SCILBAUDB 0x7753 1 SCI B Baud ...

Page 74: ...RXFFOVF RX FIFO _0 RX FIFO _1 RX FIFO _15 SCI TX Interrupt Select Logic TX EMPTY SCICTL2 6 TXINT TXRDY SCICTL2 0 TX INT ENA SCICTL2 7 To CPU AutoBaud Detect Logic TX Interrupt Logic RX Interrupt Logic SCI RX Interrupt Select Logic RXRDY SCIRXST 6 BRKDT SCIRXST 5 RX BK INT ENA SCICTL2 1 RXINT To CPU TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS...

Page 75: ...lled by clock polarity and clock phase bits include Falling edge without phase delay SPICLK active high SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal Falling edge with phase delay SPICLK active high SPI transmits data one half cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPI...

Page 76: ...s table are mapped to Peripheral Frame 2 This space only allows 16 bit accesses 32 bit accesses produce undefined results Table 4 11 SPI B Registers NAME ADDRESS SIZE x16 DESCRIPTION 1 SPICCR 0x7740 1 SPI B Configuration Control Register SPICTL 0x7741 1 SPI B Operation Control Register SPISTS 0x7742 1 SPI B Status Register SPIBRR 0x7744 1 SPI B Baud Rate Register SPIRXEMU 0x7746 1 SPI B Receive Em...

Page 77: ...y allows 16 bit accesses 32 bit accesses produce undefined results Table 4 13 SPI D Registers NAME ADDRESS SIZE x16 DESCRIPTION 1 SPICCR 0x7780 1 SPI D Configuration Control Register SPICTL 0x7781 1 SPI D Operation Control Register SPISTS 0x7782 1 SPI D Status Register SPIBRR 0x7784 1 SPI D Baud Rate Register SPIRXEMU 0x7786 1 SPI D Receive Emulation Buffer Register SPIRXBUF 0x7787 1 SPI D Serial ...

Page 78: ...I INT FLAG SPISTS 6 Receiver Overrun Flag Overrun INT ENA SPISTS 7 SPICTL 4 SPIINT SPIRXINT RX Interrupt Logic TX Interrupt Logic SPIFFOVF FLAG SPIFFRX 15 SPIDAT Data Register 16 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230N OCTOBER 2003 REVISED MAY 2012 www ti com Figure 4 14 is a block diagram of the SPI in slave mode A SPI...

Page 79: ...ransmitters and master receivers Combined master transmit receive and receive transmit mode Data transfer rate of from 10 kbps up to 400 kbps I2C Fast mode rate One 16 word receive FIFO and one 16 word transmit FIFO One interrupt that can be used by the CPU This interrupt can be generated as a result of one of the following conditions Transmit data ready Receive data ready Register access ready No...

Page 80: ...n Table 4 14 I2C A Registers NAME ADDRESS DESCRIPTION I2COAR 0x7900 I2C own address register I2CIER 0x7901 I2C interrupt enable register I2CSTR 0x7902 I2C status register I2CCLKL 0x7903 I2C clock low time divider register I2CCLKH 0x7904 I2C clock high time divider register I2CCNT 0x7905 I2C data count register I2CDRR 0x7906 I2C data receive register I2CSAR 0x7907 I2C slave address register I2CDXR ...

Page 81: ...Y 2012 4 11 GPIO MUX On the 280x the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit banging IO capability The GPIO MUX block diagram per pin is shown in Figure 4 16 Because of the open drain capabilities of the I2C pins the GPIO MUX block diagram for these pins differ See the TMS320x280x 2801x 2804x DSP System Cont...

Page 82: ...6F98 2 Reserved GPBDIR 0x6F9A 2 GPIO B Direction Register GPIO32 to 35 GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register GPIO32 to 35 0x6F9E Reserved 2 Reserved 0x6F9F 0x6FA0 Reserved 32 Reserved 0x6FBF GPIO DATA REGISTERS NOT EALLOW PROTECTED GPADAT 0x6FC0 2 GPIO Data Register GPIO0 to 31 GPASET 0x6FC2 2 GPIO Data Set Register GPIO0 to 31 GPACLEAR 0x6FC4 2 GPIO Data Clear Register GPIO0 to 31 GPATO...

Page 83: ...GPIO22 EQEP1S I O SPICLKC I O SCITXDB O 15 14 GPIO23 EQEP1I I O SPISTEC I O SCIRXDB I 17 16 GPIO24 ECAP1 I O EQEP2A I SPISIMOB I O 19 18 GPIO25 ECAP2 I O EQEP2B I SPISOMIB I O 21 20 GPIO26 ECAP3 I O EQEP2I I O SPICLKB I O 23 22 GPIO27 ECAP4 I O EQEP2S I O SPISTEB I O 25 24 GPIO28 SCIRXDA I Reserved 4 TZ5 I 27 26 GPIO29 SCITXDA O Reserved 4 TZ6 I 29 28 GPIO30 CANRXA I Reserved 4 Reserved 4 31 30 GP...

Page 84: ... Window The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals It specifies a multiple of SYSCLKOUT cycles for sampling the input signal The sampling window is either 3 samples or 6 samples wide and the output is only changed when ALL samples are the same all 0s or all 1s as shown in Figure 6 12 for 6 sample mode No Synchronization G...

Page 85: ...le TMS320F2808 Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final dev...

Page 86: ...www ti com Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is undefined Only qualified production devices are to be used TI device nomenclature also includes a suffix with the device family name Th...

Page 87: ...2804x Serial Peripheral Interface SPRUG72 0 X TMS320x28xx 28xxx Inter Integrated Circuit I2C Module SPRU721 0 X 1 A type change represents a major functional feature difference in a peripheral module Within a peripheral type there may be minor differences between devices that do not affect the basic functionality of the module These device specific differences are listed in the TMS320x28xx 28xxx D...

Page 88: ...MS320x280x 2801x 2804x Serial Communication Interface SCI Reference Guide describes the features and operation of the serial communication interface SCI module that is available on the TMS320x280x 2801x 2804x devices SPRUG72 TMS320x280x 2801x 2804x Serial Peripheral Interface Reference Guide describes how the serial peripheral interface works SPRU721 TMS320x28xx 28xxx Inter Integrated Circuit I2C ...

Page 89: ...BIOS projects are presented Example code projects are included SPRAA85 Programming TMS320x28xx and 28xxx Peripherals in C C explores a hardware abstraction layer implementation to make C C coding easier on 28x DSPs This method is compared to traditional define macros and topics of code efficiency and special case registers are also addressed SPRAA88 Using PWM Output as a Digital to Analog Converte...

Page 90: ...er to assist with C callable assembly routines SPRAA58 TMS320x281x to TMS320x280x Migration Overview describes differences between the Texas Instruments TMS320x281x and the TMS320x280x 2801x 2804x DSPs to assist in application migration Software SPRC191 C280x C2801x C C Header Files and Peripheral Examples BSDL Models SPRM244 F2809 GGM ZGM BSDL Model SPRM245 F2809 PZ BSDL Model SPRM198 F2808 100 P...

Page 91: ...Z IBIS Model SPRM404 F28016 ZGM IBIS Model SPRM403 F28015 GGM IBIS Model SPRM299 F28015 PZ IBIS Model SPRM402 F28015 ZGM IBIS Model A series of DSP textbooks is published by Prentice Hall and John Wiley Sons to support digital signal processing research and education The TMS320 DSP newsletter Details on Signal Processing is published quarterly and distributed to update TMS320 DSP customers on prod...

Page 92: ...Created to foster collaboration among engineers At e2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware an...

Page 93: ... PZ 4 40 C to 125 C Junction temperature range TJ 4 40 C to 150 C Storage temperature range Tstg 4 65 C to 150 C 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 6 2 is not implied Exposure to absolute maxim...

Page 94: ...rent VOL VOL MAX IOL Group 2 1 8 A version 40 85 C S version 40 125 Ambient temperature TA Q version 40 125 Q100 Qualification 1 Group 2 pins are as follows GPIO28 GPIO29 GPIO30 GPIO31 TDO XCLKOUT EMU0 and EMU1 6 3 Electrical Characteristics over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH IOH MAX 2 4 VOH High level output voltage V IOH 50...

Page 95: ...l loading on the I O pins 2 The IDD3VFL current indicated in this table is the flash read current and does not include additional current for erase write operations During flash programming extra current is drawn from the VDD and VDD3VFL rails as indicated in Table 6 45 If the user application involves on board flash programming this extra current must be taken into account while architecting the ...

Page 96: ...I O pins 2 The IDD3VFL current indicated in this table is the flash read current and does not include additional current for erase write operations During flash programming extra current is drawn from the VDD and VDD3VFL rails as indicated in Table 6 45 If the user application involves on board flash programming this extra current must be taken into account while architecting the power supply stag...

Page 97: ... O pins 2 The IDD3VFL current indicated in this table is the flash read current and does not include additional current for erase write operations During flash programming extra current is drawn from the VDD and VDD3VFL rails as indicated in Table 6 45 If the user application involves on board flash programming this extra current must be taken into account while architecting the power supply stage...

Page 98: ...0 μA 80 μA 120 μA 5 μA 50 μA 15 μA 30 μA Input clock is disabled 1 IDDIO current is dependent on the electrical loading on the I O pins 2 IDDA18 includes current into VDD1A18 and VDD2A18 pins In order to realize the IDDA18 currents shown for IDLE STANDBY and HALT clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register 3 IDDA33 includes current into VDDA2 and VDDAIO...

Page 99: ...le 6 5 Typical Current Consumption by Various Peripherals at 100 MHz 1 PERIPHERAL IDD CURRENT MODULE REDUCTION mA 2 ADC 8 3 I2C 5 eQEP 5 ePWM 5 eCAP 2 SCI 4 SPI 5 eCAN 11 1 All peripheral clocks are disabled upon reset Writing to reading from peripheral registers is possible only after the peripheral clocks are turned on 2 For peripherals with multiple instances the current quoted is per module Fo...

Page 100: ... Frequency F2808 Figure 6 2 Typical Operational Power Versus Frequency F2808 NOTE Typical operational current for 60 MHz devices can be estimated from Figure 6 1 For IDD current alone subtract the current contribution of non existent peripherals after scaling the peripheral currents for 60 MHz For example to compute the current of F2801 60 device the contribution by the following peripherals must ...

Page 101: ...320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230N OCTOBER 2003 REVISED MAY 2012 Figure 6 3 Typical Operational Current Versus Frequency C280x Figure 6 4 Typical Operational Power Versus Frequency C280x Copyright 2003 2012 Texas Instruments Incorporated Electrical Specifications 101 Submit Documentation Feedback Product Folder Link s ...

Page 102: ...or a single processor configuration If the distance between the JTAG header and the DSP is greater than 6 inches the emulation signals must be buffered If the distance is less than 6 inches buffering is typically not needed Figure 6 5 shows the simpler no buffering situation For the pullup pulldown resistor values see the pin description section Figure 6 5 Emulator Connection Without Signal Buffer...

Page 103: ...ycle occur with a minimum of skewing relative to each other The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles For actual cycle examples see the appropriate cycle description section of this document 6 6 2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document A Input requirements i...

Page 104: ...9 40 ns Frequency F2809 25 MHz 1 This also applies to the X1 pin if a 1 8 V oscillator is used 2 Lower LSPCLK and HSPCLK will reduce device power consumption 3 This is the default reset value if SYSCLKOUT 100 MHz Table 6 7 TMS320x280x 2801x Clock Table and Nomenclature 60 MHz Devices MIN NOM MAX UNIT tc OSC Cycle time 28 6 50 ns On chip oscillator clock Frequency 20 35 MHz tc CI Cycle time 16 67 2...

Page 105: ...e 16 67 250 C9 tf CI Fall time XCLKIN Up to 20 MHz 6 ns 20 MHz to 100 MHz 2 ns C10 tr CI Rise time XCLKIN Up to 20 MHz 6 ns 20 MHz to 100 MHz 2 ns C11 tw CIL Pulse duration XCLKIN low as a percentage of tc OSCCLK 45 55 C12 tw CIH Pulse duration XCLKIN high as a percentage of tc OSCCLK 45 55 1 This applies to the X1 pin also The possible configuration modes are shown in Table 3 17 Table 6 11 XCLKOU...

Page 106: ...ability No voltage larger than a diode drop 0 7 V above VDDIO should be applied to any digital pin for analog pins it is 0 7 V above VDDA prior to powering up the device Furthermore VDDIO and VDDA should always be within 0 3 V of each other Voltages applied to pins on an unpowered device can bias internal p n junctions in unintended ways and produce unpredictable results 6 8 1 Power Management and...

Page 107: ...er come up with a reset state of 0 SYSCLKOUT is further divided by 4 before it appears at XCLKOUT This explains why XCLKOUT OSCCLK 8 during this phase B After reset the boot ROM code samples Boot Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot code function If boot ROM code executes after power on conditions in debugger environment the boot c...

Page 108: ...12tc OSCCLK cycles watchdog td EX Delay time address data valid after XRS high 32tc OSCCLK cycles tOSCST 2 Oscillator start up time 1 10 ms th boot mode Hold time for boot mode pins 200tc OSCCLK cycles 1 In addition to the tw RSL1 requirement XRS has to be low at least for 1 ms after VDD reaches 1 5 V 2 Dependent on crystal resonator and board design A After reset the Boot ROM code samples BOOT Mo...

Page 109: ...ock up phase begins During this phase SYSCLKOUT OSCCLK 2 After the PLL lock up is complete which takes 131072 OSCCLK cycles SYSCLKOUT reflects the new operating frequency OSCCLK x 4 Figure 6 10 Example of Effect of Writing Into PLLCR Register 6 9 General Purpose Input Output GPIO 6 9 1 GPIO Output Timing Table 6 14 General Purpose Output Switching Characteristics PARAMETER MIN MAX UNIT tr GPO Rise...

Page 110: ...le mode is used D In the example shown for the qualifier to detect the change the input should be stable for 10 SYSCLKOUT cycles or greater In other words the inputs should be stable for 5 x QUALPRD x 2 SYSCLKOUT cycles This would ensure 5 sampling periods for detection to occur Since external signals are driven asynchronously an 13 SYSCLKOUT wide pulse ensures reliable recognition Figure 6 12 Sam...

Page 111: ...LPRD 0 In a given sampling window either 3 or 6 samples of the input signal are taken to determine the validity of the signal This is determined by the value written to GPxQSELn register Case 1 Qualification using 3 samples Sampling window width SYSCLKOUT cycle x 2 x QUALPRD x 2 if QUALPRD 0 Sampling window width SYSCLKOUT cycle x 2 if QUALPRD 0 Case 2 Qualification using 6 samples Sampling window...

Page 112: ...program execution resume 2 Without input qualifier 20tc SCO cycles Wake up from Flash Flash module in active state With input qualifier 20tc SCO tw IQSW td WAKE IDLE Without input qualifier 1050tc SCO cycles Wake up from Flash Flash module in sleep state With input qualifier 1050tc SCO tw IQSW Without input qualifier 20tc SCO cycles Wake up from SARAM With input qualifier 20tc SCO tw IQSW 1 For an...

Page 113: ...ule in sleep With input qualifier 1125tc SCO tw WAKE INT state Without input qualifier 100tc SCO cycles Wake up from SARAM With input qualifier 100tc SCO tw WAKE INT 1 This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction execution of an ISR triggered by the wake up signal involves additional latency A IDLE instruction is executed to put the dev...

Page 114: ...perations to flush properly C Clocks to the peripherals are turned off and the PLL is shut down If a quartz crystal or ceramic resonator is used as the clock source the internal oscillator is shut down as well The device is now in HALT mode and consumes absolute minimum power D When the GPIOn pin used to bring the device out of HALT is driven low the oscillator is turned on and the oscillator wake...

Page 115: ...t high low 20 ns tw SYNCOUT Sync output pulse width 8tc SCO cycles td PWM tza Delay time trip input active to PWM forced high no pin load 25 ns Delay time trip input active to PWM forced low td TZ PWM HZ Delay time trip input active to PWM Hi Z 20 ns 6 10 2 Trip Zone Input Timing A TZ TZ1 TZ2 TZ3 TZ4 TZ5 TZ6 B PWM refers to all the PWM pins in the device The state of the PWM pins after TZ is taken...

Page 116: ...ONS MIN MAX UNIT tw APWM Pulse duration APWMx output high low 20 ns Table 6 28 shows the eQEP timing requirement and Table 6 29 shows the eQEP switching characteristics Table 6 28 Enhanced Quadrature Encoder Pulse eQEP Timing Requirements 1 TEST CONDITIONS MIN MAX UNIT tw QEPP QEP input period Asynchronous 2 synchronous 2tc SCO cycles With input qualifier 2 1tc SCO tw IQSW tw INDEXH QEP Index Inpu...

Page 117: ...irements 1 TEST CONDITIONS MIN MAX UNIT tw INT 2 Pulse duration INT input low high Synchronous 1tc SCO cycles With qualifier 1tc SCO tw IQSW 1 For an explanation of the input qualifier parameters see Table 6 15 2 This timing is applicable to any GPIO pin configured for ADCSOC functionality Table 6 32 External Interrupt Switching Characteristics 1 PARAMETER MIN MAX UNIT td INT Delay time INT low hi...

Page 118: ...module frequency is between 1 3 μs 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately tHIGH High period of SCL clock I2C clock module frequency is between 0 6 μs 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately lI Input current with an input voltage 10 10 μA between 0 1 VDDIO and 0 9 VDDIO MAX 6 10 5 Serial Periphe...

Page 119: ... M 10 0 5tc SPC M 0 5tc LCO 10 SPICLK low clock polarity 0 5 ns tv SPCH SIMO M Valid time SPISIMO data valid after 0 5tc SPC M 10 0 5tc SPC M 0 5tc LCO 10 SPICLK high clock polarity 1 tsu SOMI SPCL M Setup time SPISOMI before SPICLK 35 35 low clock polarity 0 8 ns tsu SOMI SPCH M Setup time SPISOMI before SPICLK 35 35 high clock polarity 1 tv SPCL SOMI M Valid time SPISOMI data valid after 0 25tc ...

Page 120: ...imum before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive 0 5tc SPC after the receiving edge SPICLK of the last data bit except that SPISTE stays active between back to back transmit words in both FIFO and non FIFO modes Figure 6 20 SPI Master Mode External Timing Clock Phase 0 120 Electrical Specifications Copyright 2003 2012 Texas Instruments Incorporated Submi...

Page 121: ... SIMO M Valid time SPISIMO data valid after 0 5tc SPC M 10 0 5tc SPC M 10 SPICLK high clock polarity 0 7 ns tv SPCL SIMO M Valid time SPISIMO data valid after 0 5tc SPC M 10 0 5tc SPC M 10 SPICLK low clock polarity 1 tsu SOMI SPCH M Setup time SPISOMI before 35 35 SPICLK high clock polarity 0 10 ns tsu SOMI SPCL M Setup time SPISOMI before 35 35 SPICLK low clock polarity 1 tv SPCH SOMI M Valid tim...

Page 122: ...PC minimum before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive 0 5tc SPC after the receiving edge SPICLK of the last data bit except that SPISTE stays active between back to back transmit words in both FIFO and non FIFO modes Figure 6 21 SPI Master Mode External Timing Clock Phase 1 122 Electrical Specifications Copyright 2003 2012 Texas Instruments Incorporated...

Page 123: ...lid after SPICLK high clock polarity 1 0 75tc SPC S tsu SIMO SPCL S Setup time SPISIMO before SPICLK low clock polarity 0 35 19 ns tsu SIMO SPCH S Setup time SPISIMO before SPICLK high clock polarity 1 35 tv SPCL SIMO S Valid time SPISIMO data valid after SPICLK low clock polarity 0 0 5tc SPC S 10 20 ns tv SPCH SIMO S Valid time SPISIMO data valid after SPICLK high clock polarity 1 0 5tc SPC S 10 ...

Page 124: ... SIMO SPCH S Setup time SPISIMO before SPICLK high clock polarity 0 35 21 ns tsu SIMO SPCL S Setup time SPISIMO before SPICLK low clock polarity 1 35 tv SPCH SIMO S Valid time SPISIMO data valid after SPICLK high 0 5tc SPC S 10 clock polarity 0 22 ns tv SPCL SIMO S Valid time SPISIMO data valid after SPICLK low 0 5tc SPC S 10 clock polarity 1 1 The MASTER SLAVE bit SPICTL 2 is cleared and the CLOC...

Page 125: ...pin 0 2 or better accurate ADCREFSEL 15 14 10b 1 500 V reference recommended ADCREFSEL 15 14 01b 2 048 V AC SPECIFICATIONS SINAD 100 kHz Signal to noise ratio 67 5 dB distortion SNR 100 kHz Signal to noise ratio 68 dB THD 100 kHz Total harmonic distortion 79 dB ENOB 100 kHz Effective number of bits 10 9 Bits SFDR 100 kHz Spurious free dynamic range 83 dB 1 Tested at 12 5 MHz ADCCLK 2 All voltages ...

Page 126: ...ADC conversions are initiated 1 Timings maintain compatibility to the 281x ADC module The 280x ADC also supports driving all 3 bits at the same time and waiting td BGR ms before first conversion Table 6 40 Current Consumption for Different ADC Configurations at 12 5 MHz ADCCLK 1 2 ADC OPERATING MODE CONDITIONS VDDA18 VDDA3 3 UNIT Mode A Operational Mode 30 2 mA BG and REF enabled PWD disabled Mode...

Page 127: ...ides the reference voltages for the ADC Analog Inputs The on chip ADC consists of 16 analog inputs which are sampled either one at a time or two channels at a time These inputs are software selectable Converter The on chip ADC uses a 12 bit four stage pipeline architecture which achieves a high sample rate with low power consumption Conversion Modes The conversion can be performed in two different...

Page 128: ...lags are set a few SYSCLKOUT cycles after the Result register update The selected channels will be sampled at every falling edge of the Sample Hold pulse The Sample Hold pulse width can be programmed to be 1 ADC clock wide minimum or 16 ADC clocks wide maximum Figure 6 26 Sequential Sampling Mode Single Channel Timing Table 6 41 Sequential Sampling Mode Timing AT 12 5 MHz SAMPLE n SAMPLE n 1 ADC C...

Page 129: ... of the Sample Hold pulse The Sample Hold pulse width can be programmed to be 1 ADC clock wide minimum or 16 ADC clocks wide maximum NOTE In simultaneous mode the ADCIN channel pair select has to be A0 B0 A1 B1 A7 B7 and not in other combinations such as A1 B3 and so forth Figure 6 27 Simultaneous Sampling Mode Timing Table 6 42 Simultaneous Sampling Mode Timing AT 12 5 MHz SAMPLE n SAMPLE n 1 ADC...

Page 130: ...LSB below the nominal full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions Signal to Noise Ratio Distortion SINAD SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but exclu...

Page 131: ...ed and may affect the endurance numbers Table 6 45 Flash Parameters at 100 MHz SYSCLKOUT PARAMETER 1 TEST CONDITIONS MIN TYP MAX UNIT Program 16 Bit Word 50 μs Time 16K Sector 500 ms 8K Sector 250 ms 4K Sector 125 ms Erase 16K Sector 2 s Time 2 8K Sector 2 s 4K Sector 2 s IDD3VFLP VDD3VFL current consumption during the Erase 75 mA Erase Program cycle Program 35 mA IDDP VDD current consumption duri...

Page 132: ...sh access time 36 ns ta OTP OTP access time 60 ns Equations to compute the Flash page wait state and random wait state in Table 6 47 are as follows Equation to compute the OTP wait state in Table 6 47 is as follows Table 6 47 Minimum Required Flash OTP Wait States at Different Frequencies SYSCLKOUT FLASH PAGE FLASH RANDOM SYSCLKOUT ns OTP WAIT STATE MHz WAIT STATE WAIT STATE 1 100 10 3 3 5 75 13 3...

Page 133: ... ROM OTP area access time 1 60 ns 1 In C280x devices a 1K X 16 ROM block replaces the OTP block found in Flash devices Equations to compute the page wait state and random wait state in Table 6 49 are as follows Table 6 49 ROM ROM OTP area Minimum Required Wait States at Different Frequencies SYSCLKOUT SYSCLKOUT PAGE WAIT RANDOM WAIT MHz ns STATE STATE 1 100 10 1 1 75 13 33 1 1 50 20 0 1 30 33 33 0...

Page 134: ...fications for the Flash and ROM parts are different While migrating from Flash to ROM parts the same wait state values must be used for best performance compatibility for example in applications that use software delay loops or where precise interrupt latencies are critical The analog input switch resistance is smaller in C280x devices compared to F280x devices While migrating from a Flash to a RO...

Page 135: ... literature number SPRZ171 Section 6 8 Power Sequencing Changed Additionally it is recommended that no voltage larger than a diode drop 0 7 V should be applied to any pin prior to powering up the device to No voltage larger than a diode drop 0 7 V above VDDIO should be applied to any digital pin for analog pins it is 0 7 V above VDDA prior to powering up the device Furthermore VDDIO and VDDA shoul...

Page 136: ... PCB 48 16 40 06 37 96 35 17 ΨJT C W 0 3425 0 85 1 0575 1 410 θJC 12 89 θJB 29 58 Table 9 3 C280x Thermal Model 100 pin GGM Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA C W High k PCB 36 33 35 01 33 81 32 31 ΨJT C W 0 57 0 43 0 52 0 67 θJC 14 18 θJB 21 36 Table 9 4 C280x Thermal Model 100 pin PZ Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA C W High k PCB 69 81 60 34...

Page 137: ...l 100 pin PZ Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA C W High k PCB 44 02 28 34 36 28 33 68 ΨJT C W 0 2 0 56 0 7 0 95 θJC 7 06 θJB 28 76 Copyright 2003 2012 Texas Instruments Incorporated Mechanical Data 137 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 ...

Page 138: ...GGMA ACTIVE BGA MICROSTAR GGM 100 TBD Call TI Call TI TMS320C2802GGMS ACTIVE BGA MICROSTAR GGM 100 TBD Call TI Call TI TMS320C2802PZA ACTIVE LQFP PZ 100 TBD Call TI Call TI TMS320C2802PZQ ACTIVE LQFP PZ 100 TBD Call TI Call TI TMS320C2802PZS ACTIVE LQFP PZ 100 TBD Call TI Call TI TMS320C2802ZGMA ACTIVE BGA MICROSTAR ZGM 100 TBD Call TI Call TI TMS320C2802ZGMS ACTIVE BGA MICROSTAR ZGM 100 TBD Call ...

Page 139: ...el 2 260C 1 YEAR TMS320F2801PZS ACTIVE LQFP PZ 100 90 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR TMS320F2801PZS 60 ACTIVE LQFP PZ 100 90 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR TMS320F2801ZGMA ACTIVE BGA MICROSTAR ZGM 100 184 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR TMS320F2801ZGMS ACTIVE BGA MICROSTAR ZGM 100 184 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR TMS320F2802GGM...

Page 140: ... NIPDAU Level 2 260C 1 YEAR TMS320F2806ZGMA ACTIVE BGA MICROSTAR ZGM 100 184 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR TMS320F2806ZGMS ACTIVE BGA MICROSTAR ZGM 100 184 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR TMS320F2808GGMA ACTIVE BGA MICROSTAR GGM 100 184 TBD SNPB Level 3 220C 168 HR TMS320F2808GGMS ACTIVE BGA MICROSTAR GGM 100 184 TBD SNPB Level 3 220C 168 HR TMS320F2808PZA ACTIVE LQ...

Page 141: ...nned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements f...

Page 142: ...ing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis ...

Page 143: ...L GRID ARRAY 0 08 0 10 1 40 MAX 0 85 0 55 0 45 0 45 0 35 0 95 4 C B A D E 2 1 3 K F G H J 5 7 6 9 8 10 Seating Plane SQ 9 90 10 10 7 20 TYP 0 40 0 40 A1 Corner Bottom View 4145257 3 C 12 01 0 80 0 80 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C MicroStar BGA configuration ...

Page 144: ......

Page 145: ...QUAD FLATPACK 4040149 B 11 96 50 26 0 13 NOM Gage Plane 0 25 0 45 0 75 0 05 MIN 0 27 51 25 75 1 12 00 TYP 0 17 76 100 SQ SQ 15 80 16 20 13 80 1 35 1 45 1 60 MAX 14 20 0 7 Seating Plane 0 08 0 50 M 0 08 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 ...

Page 146: ......

Page 147: ...regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequence...

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