Texas Instruments TMS320F280049C, User Manual

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Table 4-4. User-Adjustable Resistor Divider Settings for DRV8316T Variant (defaults in bold) (continued)
Setting Name Description Resistors
(AVDD/ AGND) Hardware Setting
SLEW Slew rate Phase pin slew rate switching low
to high (10-90%) and high to low
(90-10%) R38/R43 Tied to AGND 25 V/µs
Hi-Z 50 V/µs
47 kΩ to AVDD 125 V/µs
Tied to AVDD 200 V/µs
OCP/SR Overcurrent
Protection / Smart
Rectification Selects the Mode for Overcurrent
and Smart Rectification Settings
(ASR = Automatic Synchronous
Rectification; AAR = Automatic
Asynchronous Rectification) R41/R46 Tied to AGND OCP = 10 A
ASR and AAR
Disabled
22 kΩ to AGND OCP = 15 A
ASR and AAR
Disabled
100 kΩ to AGND OCP = 10 A
ASR Enabled
Hi-Z OCP = 10 A
ASR and AAR
Enabled
100 kΩ to AVDD OCP = 15 A
ASR Enabled
22 kΩ to AVDD OCP = 15 A
ASR and AAR
Enabled
Tied to AVDD OCP = 15 A
ASR and AAR
Enabled
GAIN G
CSA
Current sense gain R39/R44 Tied to AGND 0.15 V/A
Hi-Z 0.3 V/A
47 kΩ to AVDD 0.6 V/A
Tied to AVDD 1.2 V/A
4.4 Interfacing DRV8316REVM and LAUNCHXL-F280049C LaunchPad ™
The DRV8316REVM has 40 pins with different functions. These pins are interfaced with the LAUNCHXL-
F280049C LaunchPad development kit and are mapped appropriately to receive the functionalities of the
DRV8316R device. These 40 pins are grouped into 4 ports in respect to the LAUNCHXL-F280049C (J1 to J4).
Table 4-5 and Table 4-6 list the interfacing of these ports of the DRV8316REVM headers J3 and J4.
Table 4-5. Connections for Header J3 on DRV8316REVM (DNP in bold)
J3 Pin
Number
DRV8316REVM
Function LAUNCHXL-F280049C
Function Description
1 3.3VBK (DNP) 3.3 V 3.3-V LaunchPad supply
2 Not used 5 V 5-V LaunchPad supply
3 Not used PGA1/3/5_GND Not used
4 AGND GND GND connection
5 Not used GPIO13/SCIBRX Not used
6 VSENA ADCINA5 Phase A Voltage Sense
7 Not used GPIO40/SCIBTX Not used
8 VSENB ADCINB0 Phase B voltage sense
9 nSLEEP (DNP) NC For internal use only
10 VSENC ADCINC2 Phase C voltage sense
11 Not used ADCINB3/VDAC Not used
12 VSENVM ADCINB1 VM Bus voltage sense
13 SCLK SPIACLK SPI clock (DRV8316R only)
14 ISENA ADCINB2 Phase A current sense
Hardware and Software Overview www.ti.com
12 DRV8316REVM Evaluation Module SLVUBZ9A – DECEMBER 2020 – REVISED FEBRUARY 2021
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