10.3.3 Max Reset
10.3.4 System Reset
10.3.5 Module Reset
10.4 Default Device Configurations
10.4.1 Device Configuration Pins
Default Device Configurations
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Max reset is like warm reset, except max reset is initiated by the Watchdog Timer (WDT) or by an IcePick
emulation command. For debug, max reset allows an ARM emulator to initiate chip reset using an IcePick
emulation command while remaining active during and after the reset sequence.
The following steps describe the max reset sequence:
1. To initiate max reset, the WDT expires (indicating a runaway condition) or the ARM emulator initiates a
max reset command via the IcePick emulation module.
2. Hardware latches the device configuration pins on the rising edge of RESETN. The device
configuration pins allow you to set several options at reset. See
for more information.
3. Hardware resets all modules including memories, but not ARM emulation circuitry.
4. Warm reset finishes, all modules except ARM emulation are in their default configurations, and
hardware begins the boot process.
Note:
Max reset may be blocked by an emulator command. This allows an emulator to block a
WDT initiated max reset for debug purposes.
For information on the WDT, see the
TMS320DM335 Digital Media System-on-Chip (DMSoC) Timer /
Watchdog Timer Reference Guide
(
) . See
for information on IcePick emulation.
The emulator initiates system reset via the ICECrusher emulation module. It is considered a soft reset
(i.e., memory is not reset). None of the following modules are reset: DDR EMIF, PLL Controller (PLLC),
Power and Sleep Controller (PSC), and emulation.
The following steps describe the system reset sequence:
1. The emulator initiates system reset.
2. The proper modules are reset.
3. The system reset finishes, the proper modules are reset, and the CPU is out of reset.
Module reset allows you to independently reset a module using the ARM software. You can use module
reset to return a module to its default state (i.e., its state as seen after POR, warm reset, and max reset).
Module reset is intended as a debug tool; it is not necessarily intended as a tool for use in production.
The procedures for asserting and de-asserting module reset are fully described in
After POR, warm reset, and max reset, the chip is in its default configuration. This section highlights the
default configurations associated with PLLs, clocks, ARM boot mode, and AEMIF.
Note:
Default configuration is the configuration immediately after POR, warm reset, and max reset
and just before the boot process begins. The boot ROM updates the configuration. See
for more information on the boot process.
The device configuration pins are described in
. The device configuration pins are latched at
reset and allow you to configure all of the following options at reset:
•
ARM Boot Mode
•
Asynchronous EMIF pin configuration
These pins are described further in the following sections.
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Reset
SPRUFX7 – July 2008
