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2.5 Program Cache

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

SPRS268E – MAY 2005 – REVISED JANUARY 2007

The C672x DSP executes code directly from a large on-chip 32K-byte program cache. The program cache
has these key features:

•

Wide 256-bit path to internal ROM/RAM

•

Single-cycle access on cache hits

•

2-cycle miss penalty to internal ROM/RAM

•

Caches external memory as well as ROM/RAM

•

Direct-mapped

•

Modes: Enable, Freeze, Bypass

•

Software invalidate to support code overlay

The program cache line size is 256 bits wide and is matched with a 256-bit-wide path between cache and
internal memory. This allows the program cache to fill an entire line (corresponding to eight C67x+ CPU
instructions) with only a single miss penalty of 2 cycles.

The program cache control registers are listed in

Table 2-4

.

Table 2-4. Program Cache Control Registers

REGISTER NAME

BYTE ADDRESS

DESCRIPTION

L1PISAR

0x2000 0000

L1P Invalidate Start Address

L1PICR

0x2000 0004

L1P Invalidate Control Register

CAUTION

Any application which modifies the contents of program RAM (for example, a program
overlay) must invalidate the addresses from program cache to maintain coherency by
explicitly writing to the L1PISAR and L1PICR registers.

The Cache Mode (Enable, Freeze, Bypass) is configured through a CPU internal register (CSR, bits 7:5).
These options are listed in

Table 2-5

. Typically, only the Cache Enable Mode is used. But advanced users

may utilize Freeze and Bypass modes to tune performance.

Table 2-5. Cache Modes Set Through PCC Field of CSR CPU Register on C672x

CPU CSR[7:5]

CACHE MODE

000b

Enable (Deprecated - Means direct mapped RAM on some C6000 devices)

010b

Enable - Cache is enabled, cache misses cause a line fill.

011b

Freeze - Cache is enabled, but contents are unchanged by misses.

100b

Bypass - Forces cache misses, cache contents frozen.

Other Values

Reserved - Not Supported

CAUTION

Although the reset value of CSR[7:5] (PCC field) is 000b, the value may be modified
during the boot process by the ROM code. Refer to the appropriate ROM data sheet
for more details. However, note that the cache may be disabled when control is
actually passed to application code. Therefore, it may be necessary to write '010b' to
the PCC field to explicitly enable the cache at the start of application code.

CAUTION

Changing the cache mode through CSR[7:5] does not invalidate any lines already in
the cache. To invalidate the cache after modifications are made to program space, the
control registers L1PISAR and L1PICR must be used.

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Device Overview

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Summary of Contents for TMS320C6722

Page 1: ...ossbar Switch Instrument Amp Modeling Dedicated McASP DMA Bus Audio Conferencing Deterministic I O Performance Audio Broadcast dMAX Dual Data Movement Accelerator Audio Encoder Supports Emerging Audio Applications 16 Independent Channels Biometrics Concurrent Processing of Two Transfer Medical Requests Industrial 1 2 and 3 Dimensional Commercial or Extended Temperature Memory to Memory and Memory ...

Page 2: ... crossbar switch acts as a central hub between the different bus masters CPU dMAX UHPI and different targets peripherals and memory The crossbar is partially connected some connections are not supported for example UHPI to peripheral connections Multiple transfers occur in parallel through the crossbar as long as there is no conflict between bus masters for a particular target When a conflict does...

Page 3: ...e slots Each McASP includes a transmit and receive section which may operate independently or synchronously furthermore each section includes its own flexible clock generator and extensive error checking logic As data passes through the McASP it can be realigned so that the fixed point representation used by the application code can be independent of the representation used by the external devices...

Page 4: ...MHz to 25 MHz Alternatively the clock can be provided externally through the CLKIN pin The DSP includes a flexible software programmable phase locked loop PLL clock generator Three different clock domains SYSCLK1 SYSCLK2 and SYSCLK3 are generated by dividing down the PLL output SYSCLK1 is the clock used by the CPU memory controller and memories SYSCLK2 is used by the peripheral subsystem and dMAX ...

Page 5: ...Bus EMIF 32 Events In 32 MAX1 MAX0 32 CONTROL 32 Interrupts Out I O dMAX McASP0 16 Serializers McASP1 6 Serializers McASP2 2 Serializers DIT SPI1 SPI0 I2C1 I2C0 RTI 32 UHPI PLL Peripheral Interrupt and DMA Events 32 32 32 32 32 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 1 1 shows the functional block diagram of the C67...

Page 6: ...dio Serial Ports McASP0 McASP1 and McASP2 68 2 5 Program Cache 11 4 14 Serial Peripheral Interface Ports SPI0 SPI1 80 2 6 High Performance Crossbar Switch 12 4 15 Inter Integrated Circuit Serial Ports I2C0 I2C1 93 2 7 Memory Map Summary 15 4 16 Real Time Interrupt RTI Timer With Digital 2 8 Boot Modes 16 Watchdog 97 2 9 Pin Assignments 19 4 17 External Clock Input From Oscillator or CLKIN Pin 100 ...

Page 7: ... On Chip Memory Size KB 256KB RAM 256KB RAM 128KB RAM 384KB ROM 384KB ROM 384KB ROM Control Status Register CPU ID CPU Rev ID 0x0300 CSR 31 16 Frequency MHz 300 250 250 225 250 225 200 3 3 ns C6727 300 4 ns C6722 250 4 ns C6726 250 Cycle Time ns 4 ns C6727A 250 and 4 4 ns C6722A 225 4 4 ns C6726A 225 C6727 250 5 ns C6722 200 Core V 1 2 V Voltage I O V 3 3 V Prescaler 1 2 3 32 Clock Generator Optio...

Page 8: ...icated for multiplies and the S and L functional units perform a general set of arithmetic logical and branch functions All instructions operate on registers as opposed to data in memory but results stored in the 32 bit registers can be subsequently moved to memory as bytes half words or words Figure 2 1 CPU Data Paths The register file in each data path contains 32 32 bit registers for a total of...

Page 9: ...ed the interrupt channel is shared and an interrupt on this channel could have come from any of the enabled peripherals on that channel The dMAX peripheral has two CPU interrupts dedicated to reporting FIFO status INT7 and transfer completion INT8 In addition the dMAX can generate interrupts to the CPU on lines INT9 13 and INT15 in response to peripheral events To enable this functionality the ass...

Page 10: ...internal RAM and ROM from three of the following four sources as long as there are no bank conflicts Two 64 bit data accesses from the C67x CPU One 256 bit wide program fetch from the program cache One 32 bit data access from the peripheral system either dMAX or UHPI A program cache miss is 256 bits wide and conflicts only with data accesses to the same page Multiple data accesses to different pag...

Page 11: ...ency by explicitly writing to the L1PISAR and L1PICR registers The Cache Mode Enable Freeze Bypass is configured through a CPU internal register CSR bits 7 5 These options are listed in Table 2 5 Typically only the Cache Enable Mode is used But advanced users may utilize Freeze and Bypass modes to tune performance Table 2 5 Cache Modes Set Through PCC Field of CSR CPU Register on C672x CPU CSR 7 5...

Page 12: ...ority Config dMAX T5 M3 M4 External Host MCU Config ROM RAM CPU Program Cache Crossbar TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 The C672x DSP includes a high performance crossbar switch that acts as a central hub between bus masters and targets Figure 2 4 illustrates the connectivity of the crossbar switch Figure 2 4 Block ...

Page 13: ...CSP CPU fills program cache from EMIF Example 2 Conflict over a shared resource dMAX HiMAX accesses RTI port for McASP sample rate measurement dMAX LoMAX accesses SPI port for control processing In Example 2 both masters contend for the same target the peripheral configuration bus The HiMAX access will be given priority over the LoMAX access The master priority is illustrated in Figure 2 4 by the ...

Page 14: ...E Register Bit Layout 0x4000 0024 Table 2 7 CFGBRIDGE Register Bit Field Description 0x4000 0024 BIT NO NAME RESET VALUE READ WRITE DESCRIPTION 31 1 Reserved N A N A Reads are indeterminate Only 0s should be written to these bits 0 CSPRST 1 R W Resets the CSP Bridge BR2 in Figure 2 4 1 Bridge Reset Asserted 0 Bridge Reset Released CAUTION The CSPRST bit must be asserted after any change to the PLL...

Page 15: ...ers 0x4500 0000 0x4500 02BF Word Only McASP2 Control Registers 0x4600 0000 0x4600 02BF Word Only SPI0 Control Registers 0x4700 0000 0x4700 007F Word Only SPI1 Control Registers 0x4800 0000 0x4800 007F Word Only I2C0 Control Registers 0x4900 0000 0x4900 007F Word Only I2C1 Control Registers 0x4A00 0000 0x4A00 007F Word Only McASP0 DMA Port any address in this range 0x5400 0000 0x54FF FFFF Word Only...

Page 16: ...nor a RTI reset causes these registers to update The ROM bootmodes include Parallel Flash on EM_CS 2 SPI0 or I2C1 master mode from serial EEPROM SPI0 or I2C1 slave mode from external MCU UHPI from an external MCU Table 2 9 describes the required boot pin settings at device reset for each bootmode Table 2 9 Required Boot Pin Settings at Device Reset BOOT MODE UHPI_HCS SPI0_SOMI SPI0_SIMO SPI0_CLK U...

Page 17: ...Reserved Reads are indeterminate Only 0s should be written to these bits 7 PINCAP7 SPI0_SOMI I2C0_SDA pin state captured on rising edge of RESET pin 6 PINCAP6 SPI0_SIMO pin state captured on rising edge of RESET pin 5 PINCAP5 SPI0_CLK I2C0_SCL pin state captured on rising edge of RESET pin 4 PINCAP4 SPI0_SCS I2C1_SCL pin state captured on rising edge of RESET pin 3 PINCAP3 SPI0_ENA I2C1_SDA pin st...

Page 18: ... BIT NO NAME DESCRIPTION 31 8 Reserved Reads are indeterminate Only 0s should be written to these bits 7 PINCAP15 AXR0 5 SPI1_SCS pin state captured on rising edge of RESET pin 6 PINCAP14 AXR0 6 SPI1_ENA pin state captured on rising edge of RESET pin 5 PINCAP13 UHPI_HCS pin state captured on rising edge of RESET pin 4 PINCAP12 UHPI_HD 0 pin state captured on rising edge of RESET pin 3 PINCAP11 EM_...

Page 19: ... CVDD CVDD CVDD VSS VSS DVDD DVDD DVDD DVDD DVDD VSS EM_D 2 HA 0 EM_D 16 UHPI_ HA 15 EM_D 31 UHPI_ EM_D 3 EM_D 4 HA 1 EM_D 17 UHPI_ HA 2 EM_D 18 UHPI_ EM_D 5 EM_D 6 HA 3 EM_D 19 UHPI_ EM_D 7 EM_WE_ DQM 0 HA 4 EM_D 20 UHPI_ HA 6 EM_D 22 UHPI_ HD 29 UHPI_ TRST OSCVDD HD 31 UHPI_ HD 18 UHPI_ UHPI_ HD 20 HRDY UHPI_ HDS 1 UHPI_ HRW UHPI_ HCNTL 0 UHPI_ HBE 2 UHPI_ HBE 1 UHPI_ HBE 0 UHPI_ HDS 2 UHPI_ HCS...

Page 20: ...BA 0 V SS EM_BA 1 EM_A 10 DV DD EM_A 0 CV DD EM_A 1 EM_A 2 V SS EM_A 3 CV DD EM_A 4 EM_A 5 V SS DV DD EM_A 6 V SS CV DD EM_A 8 EM_A 9 EM_A 11 DV DD VSS SPI0_SIMO SPI0_SOMI I2C0_SDA DVDD AXR0 0 VSS AXR0 1 AXR0 2 AXR0 3 VSS AXR0 4 AXR0 5 SPI1_SCS AXR0 6 SPI1_ENA AXR0 7 SPI1_CLK CVDD VSS DVDD AXR0 8 AXR1 5 SPI1_SOMI AXR0 9 AXR1 4 SPI1_SIMO CVDD VSS AXR0 10 AXR1 3 AXR0 11 AXR1 2 CVDD VSS AXR0 12 AXR1 ...

Page 21: ...Address EM_BA 1 94 H16 O N EM_CS 0 97 F15 O N SDRAM Chip Select EM_CS 2 100 E15 O N Asynchronous Memory Chip Select EM_CAS 37 R3 O N SDRAM Column Address Strobe EM_RAS 98 F16 O N SDRAM Row Address Strobe EM_WE 38 T3 O N SDRAM Asynchronous Write Enable EM_CKE 71 T14 O N SDRAM Clock Enable EM_CLK 70 R14 O N EMIF Output Clock EM_WE_DQM 0 39 R4 O N Write Enable or Byte Enable for EM_D 7 0 EM_WE_DQM 1 ...

Page 22: ... 63 R12 IO N EM_D 11 61 T11 IO N EM_D 12 59 R11 IO N EM_D 13 58 R10 IO N EM_D 14 56 T9 IO N EM_D 15 55 R9 IO N EM_D 16 UHPI_HA 0 N7 IO I IPD N EM_D 17 UHPI_HA 1 P6 IO I IPD N EM_D 18 UHPI_HA 2 N6 IO I IPD N EM_D 19 UHPI_HA 3 P5 IO I IPD N EM_D 20 UHPI_HA 4 P4 IO I IPD N EM_D 21 UHPI_HA 5 P3 IO I IPD N EM_D 22 UHPI_HA 6 N4 IO I IPD N EM_D 23 UHPI_HA 7 R2 IO I IPD N EMIF Data Bus Upper 16 Bits IO or...

Page 23: ...exed UHPI_HD 23 C3 IO IPD Y UHPI_HHWIL I on pin UHPI_HD 16 HHWIL and GPIO UHPI_HD 24 P2 IO IPD Y on other pins in the following mode UHPI_HD 25 N2 IO IPD Y Half word Multiplexed Address and Data UHPI_HD 26 N3 IO IPD Y In this mode UHPI_HHWIL indicates whether the high or low half word is being addressed UHPI_HD 27 M3 IO IPD Y UHPI_HD 28 L3 IO IPD Y UHPI_HD 29 L4 IO IPD Y UHPI_HD 30 L2 IO IPD Y UHP...

Page 24: ...XR1 3 130 B8 IO Y McASP0 Serial Data 10 or McASP1 Serial Data 3 AXR0 11 AXR1 2 131 A8 IO Y McASP0 Serial Data 11 or McASP1 Serial Data 2 AXR0 12 AXR1 1 134 B7 IO Y McASP0 Serial Data 12 or McASP1 Serial Data 1 AXR0 13 AXR1 0 135 B6 IO Y McASP0 Serial Data 13 or McASP1 Serial Data 0 AXR0 14 AXR2 1 137 A6 IO Y McASP0 Serial Data 14 or McASP2 Serial Data 1 4 AXR0 15 AXR2 0 138 B5 IO Y McASP0 Serial D...

Page 25: ...lect TDI 28 L1 I IPU N Test Data In TDO 29 M2 OZ IPU N Test Data Out TRST 21 K4 I IPD N Test Reset EMU 0 32 M1 IO IPU N Emulation Pin 0 EMU 1 34 N1 IO IPU N Emulation Pin 1 Power Pins 256 Terminal GDH ZDH Package Core Supply CVDD E6 E7 E8 E9 E10 E11 G5 G12 H5 H12 J5 J12 K5 K12 M6 M7 M8 M9 M10 M11 IO Supply DVDD A2 A15 B1 B16 D4 D5 D12 D13 E4 E13 J14 M4 M13 N5 N12 P8 R1 R16 T2 T15 A1 A7 A10 A16 E5 ...

Page 26: ...0 2 1 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all DSP devices and support tools Each DSP commercial family member has one of three prefixes TMX TMP or TMS e g TMS320C6727GDH250 Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These pr...

Page 27: ... MHz CPU TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is undefined Only qualif...

Page 28: ...atform This document also describes operations and registers unique to the dMAX controller SPRAA78 TMS320C6713 to TMS320C672x Migration This document describes the issues related to migrating from the TMS320C6713 to TMS320C672x digital signal processor DSP SPRU711 TMS320C672x DSP External Memory Interface EMIF User s Guide This document describes the operation of the external memory interface EMIF...

Page 29: ... examples and discusses optimizations for the assembly code and describes programming considerations for the C64x DSP SPRU186 TMS320C6000 Assembly Language Tools v6 0 Beta User s Guide Describes the assembly language tools assembler linker and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the TMS320C60...

Page 30: ...0x4000 0014 Selects the sources for the RTI Input Captures from among the six Table 4 37 McASP DMA events CFGMCASP0 0x4000 0018 Selects the peripheral pin to be used as AMUTEIN0 Table 4 19 CFGMCASP1 0x4000 001C Selects the peripheral pin to be used as AMUTEIN1 Table 4 20 CFGMCASP2 1 0x4000 0020 Selects the peripheral pin to be used as AMUTEIN2 Table 4 21 CFGBRIDGE 0x4000 0024 Controls reset of the...

Page 31: ... and UHPI pins Table 3 4 Options for Configuring EMIF and UHPI C6727 Only CONFIGURATION OPTION 1 OPTION 2 PERIPHERAL UHPI Multiplexed Address Data Mode Fullword or Non Multiplexed Address Data Mode Half Word Fullword EMIF 32 bit EMIF Data 16 bit EMIF Data PINS EM_D 31 16 EM_D 31 16 UHPI_HA 15 0 UHPI_HA 15 0 While Section 3 2 describes at a high level the most common pin multiplexing options the co...

Page 32: ... AXR0 10 AXR1 3 AXR0 10 AXR1 3 AXR0 11 AXR1 2 AXR0 11 AXR1 2 AXR0 12 AXR1 1 AXR0 12 AXR1 1 AXR0 13 AXR1 0 AXR0 13 AXR1 0 AXR0 14 AXR2 1 AXR0 14 AXR2 1 AXR0 15 AXR2 0 AXR0 15 AXR2 0 AHCLKR0 AHCLKR1 AHCLKR0 AHCLKR1 AHCLKX0 AHCLKX2 AHCLKX0 AHCLKX2 AMUTE2 HINT AMUTE2 HINT HD 16 HHWIL HD 16 HHWIL EM_D 31 16 UHPI_HA 15 0 1 EM_D 31 16 Disabled if UHPI_HA 15 0 Input Only CFGHPI NMUX 1 1 When using the UHP...

Page 33: ...3 to CVDD 0 5 Clamp Current 20 mA Operating case temperature range TC Default 0 to 90 C A version 40 to 105 Storage temperature range Tstg 65 to 150 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating...

Page 34: ...ins with internal pullup 50 170 µA Pins with internal pulldown 50 170 ttr Input Transition Time 25 ns CI Input Capacitance 7 pF CO Output Capacitance 7 pF IDD2V CVDD Supply 1 GDH CVDD 1 2 V 658 CPU clock 300 MHz mA RFP CVDD 1 2 V 555 CPU clock 250 MHz IDD3V DVDD Supply 1 GDH DVDD 3 3 V 76 32 bit EMIF speed 100 MHz mA RFP DVDD 3 3 V 58 16 bit EMIF speed 100 MHz 1 Assumes the following conditions 25...

Page 35: ...line is intended as a load only It is not neccessary to add or subtract the transmission line delay 2 ns or longer from the data sheet timings Input requirements in this data sheet are tested with an input slew rate of 4 Volts per nanosecond 4 V ns at the device pin Figure 4 1 Test Load Circuit for AC Timing Measurements 4 5 1 1 Signal Transition Levels All input and output timing parameters are r...

Page 36: ...en the symbols some of the pin names and other related terminology have been abbreviated as follows Lowercase subscripts and their meanings Letters and symbols and their meanings a access time H High c cycle time period L Low d delay time V Valid dis disable time Z High impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration width ...

Page 37: ...In order to properly decouple the supply planes from system noise place as many capacitors caps as possible close to the DSP The core supply caps can be placed in the interior space of the package and the I O supply caps can be placed around the exterior space of the package For the BGA package it is recommended that both the core and I O supply caps be placed on the underside of the PCB For the T...

Page 38: ...have reached their proper operating conditions As a best practice RESET should be held low during power up Prior to deasserting RESET low to high transition the core and I O voltages should be at their proper operating conditions Table 4 1 assumes testing over recommended operating conditions Table 4 1 Reset Timing Requirements NO MIN MAX UNIT 1 tw RSTL Pulse width RESET low 100 ns 2 tsu BPV RSTH ...

Page 39: ...luding internal memory peripherals and external memory The dMAX controller in the C672x DSP has a different architecture from the previous EDMA controller in the C621x C671x devices The dMAX controller includes features such as capability to perform three dimensional data transfers for advanced data sorting capability to manage a section of the memory as a circular buffer FIFO with delay tap based...

Page 40: ...nsfer Entry 0 Event Entry 31 Reserved Event Table Entry Event Entry k Event Entry 0 High Priority REQ Low Priority REQ High Priority PaRAM To From Crossbar Switch LoMAX Master Crossbar Switch Port Events Interrupt Lines to the CPU HiMAX Master Crossbar Switch Port dMAX Low Priority PaRAM TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY ...

Page 41: ...pes or to an interrupt In case an event entry associates the event to one of the transfer types the event entry will contain a pointer to the specific transfer entry in the transfer entry table The transfer table may contain up to eight transfer entries A transfer entry specifies details required by the dMAX controller to perform the transfer In case an event entry associates the event to an inter...

Page 42: ...T 13 SPI0RX SPI0 DMA_RX_REQ 14 SPI1RX SPI1 DMA_RX_REQ 15 RTIREQ2 RTI DMA REQ 2 16 RTIREQ3 RTI DMA REQ 3 17 DETR 2 The CPU triggers the event by creating appropriate transition edge on bit2 in DETR register 18 DETR 18 The CPU triggers the event by creating appropriate transition edge on bit18 in DETR register 19 I2C0XEVT I2C 0 Transmit Event 20 I2C0REVT I2C 0 Receive Event 21 I2C1XEVT I2C 1 Transmi...

Page 43: ...R Event High priority Register 0x6000 0018 DELPR Event Low priority Register 0x6000 001C DEFR Event Flag Register 0x6000 0034 DER0 Event Register 0 0x6000 0054 DER1 Event Register 1 0x6000 0074 DER2 Event Register 2 0x6000 0094 DER3 Event Register 3 0x6000 0040 DFSR0 FIFO Status Register 0 0x6000 0060 DFSR1 FIFO Status Register 1 0x6000 0080 DTCR0 Transfer Complete Register 0 0x6000 00A0 DTCR1 Tra...

Page 44: ...red as a general purpose input pin within the associated peripheral Also the AMUTEIN signal should be disabled within the corresponding McASP so that AMUTE is not driven when AMUTEIN is active This can be done by clearing the INEN bit of the AMUTE register inside the McASP Finally AMUTEIN events are logically ORed with the McASP transmit and receive error events within the dMAX therefore the ISR t...

Page 45: ...res illustrate the C672x DSP includes a limited number of EMIF address lines These are sufficient to connect to SDRAM seamlessly Asynchronous memory such as FLASH typically will need to use additional GPIO pins to act as upper address lines during device boot up when the FLASH contents are copied into SDRAM Normally code is executed from SDRAM since SDRAM has faster access times Any pins listed wi...

Page 46: ...8 13 RY BY RESET OE WE CE DQ 15 0 512K x 16 A 0 A 12 1 FLASH EM_BA 1 RESET Any GPIO capable pins which can be pulled down at reset can be used to control A 18 13 for FLASH BOOTLOAD Examples AHCLKR0 SPI0_SCS SCL1 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 5 C6726 C6722 DSP 16 Bit EMIF Example Peripheral and Electrical...

Page 47: ...Any GPIO capable pins which can be pulled down at reset can be used to control A 18 14 for FLASH BOOTLOAD Examples AHCLKR0 SPI0_SCS SCL1 EM_WE_DQM 3 EM_D 31 16 UHPI_HA 15 0 EM_CS 2 EM_RW EM_OE EM_WAIT BA 1 0 A 12 0 DQ 15 0 LDQM UDQM 4M x 16 x 4 Bank RAS CLK CKE WE CAS CE SDRAM TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure...

Page 48: ...n Register 0xF000 0008 SDCR SDRAM Configuration Register 0xF000 000C SDRCR SDRAM Refresh Control Register 0xF000 0010 A1CR Asynchronous 1 Configuration Register 0xF000 0020 SDTIMR SDRAM Timing Register 0xF000 003C SDSRETR SDRAM Self Refresh Exit Timing Register 0xF000 0040 EIRR EMIF Interrupt Raw Register 0xF000 0044 EIMR EMIF Interrupt Mask Register 0xF000 0048 EIMSR EMIF Interrupt Mask Set Regis...

Page 49: ...id 7 7 ns 6 toh EM_CLKH EM_WE DQMIV S Output hold time EM_CLK rising to EM_WE_DQM 3 0 invalid 1 15 ns 7 td EM_CLKH EM_AV S Delay time EM_CLK rising to EM_A 12 0 and EM_BA 1 0 valid 7 7 ns Output hold time EM_CLK rising to EM_A 12 0 and EM_BA 1 0 8 toh EM_CLKH EM_AIV S 1 15 ns invalid 9 td EM_CLKH EM_DV S Delay time EM_CLK rising to EM_D 31 0 valid 7 7 ns 10 toh EM_CLKH EM_DIV S Output hold time EM...

Page 50: ...t also be met in order to ensure the EM_WAIT signal is correctly sampled 4 In Figure 4 13 it appears that there are more than 4 EM_CLK cycles encompassed by parameter 35 However EM_CLK cycles that are part of the extended wait period should not be counted the 4 EM_CLK requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles Table 4 8 EMIF Asynchronous I...

Page 51: ... 1 2 2 4 6 8 8 12 14 19 20 3 5 7 7 11 13 17 18 2 EM_CLK Delay BASIC SDRAM READ OPERATION EM_CS 0 EM_WE_DQM 3 0 EM_RAS EM_CAS EM_WE TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 7 Basic SDRAM Write Operation Figure 4 8 Basic SDRAM Read Operation Submit Documentation Feedback Peripheral and Electrical Specifications 51 ...

Page 52: ... SETUP STROBE HOLD TA 22 23 23 25 25 22 23 23 28 29 21 21 17 18 BYTE LANE ENABLES ADDRESS ADDRESS ASYNCHRONOUS READ SELECT STROBE MODE EM_CS 2 EM_WE_DQM 3 0 EM_OE EM_WE EM_RW TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 9 Asynchronous Read WE Strobe Mode Figure 4 10 Asynchronous Read Select Strobe Mode Peripheral and E...

Page 53: ...0 SETUP STROBE HOLD 22 23 23 32 32 23 23 26 26 24 22 21 21 27 ASYNCHRONOUS WRITE SELECT STROBE MODE BYTE LANE ENABLES ADDRESS ADDRESS WRITE DATA EM_CS 2 EM_WE_DQM 3 0 EM_OE EM_WE EM_RW TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 11 Asynchronous Write WE Strobe Mode Figure 4 12 Asynchronous Write Select Strobe Mode Sub...

Page 54: ...E EXTENDED WAIT STATES 34 35 30 31 33 33 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 13 EM_WAIT Timing Requirements 54 Peripheral and Electrical Specifications Submit Documentation Feedback ...

Page 55: ...ontrol signals on its falling edge and write data on its rising edge The UHPI_HCS signal also gates the deassertion of the UHPI_HRDY signal externally Figure 4 14 UHPI Strobe and Ready Interaction The two HPI control pins UHPI_HCNTL 1 0 determine the type of access that the host will perform Note that only two of the four access types are supported in Non Multiplexed Host Address Data Fullword Mod...

Page 56: ... Data Fullword mode the UHPI can be made more secure by restricting the upper 16 bits of the DSP addresses it can access to what is set in CFGHPIAMSB and CFGHPIAUMB registers See Table 4 13 and Table 4 14 The host is responsible for configuring the internal HPIA register whether or not it is being overridden by the device configuration registers CFGHPIAMSB and CFGHPIAUMB After the HPIA register ha...

Page 57: ...ternal host microcontroller In this mode all 32 bits of UHPI_HD 31 0 are used and the host can access HPIA HPID and HPIC in a single bus cycle A May be used as EM_D 31 16 B Optional for hosts supporting multiplexed address and data Pull up if not used Low when address is on the bus C Two host address lines or host GPIO if address lines are not available D Byte Enables active during reads and write...

Page 58: ...Two host address lines or host GPIO if address lines are not available B Not used in this mode C Byte Enables active during reads and writes Some processors support a byte enable mode on their write enable pins D Only required if needed for strobe timing Not required if CS meets strobe timing requirements Figure 4 17 UHPI Non Multiplexed Host Address Data Fullword Mode CAUTION The EMIF data bus an...

Page 59: ...ation Management Register 0x4300 0008 GPIOINT General Purpose I O Interrupt Control Register 0x4300 000C GPIOEN General Purpose I O Enable Register 0x4300 0010 GPIODIR1 General Purpose I O Direction Register 1 0x4300 0014 GPIODAT1 General Purpose I O Data Register 1 0x4300 0018 GPIODIR2 General Purpose I O Direction Register 2 0x4300 001C GPIODAT2 General Purpose I O Data Register 2 0x4300 0020 GP...

Page 60: ... is a word address 1 Host Address is a byte address 3 FULL 0 R W UHPI Multiplexing Mode when NMUX 0 0 Half Word 16 bit data Multiplexed Address and Data Mode 1 Fullword 32 bit data Multiplexed Address and Data Mode 2 NMUX 0 R W UHPI Non Multiplexed Mode Enable 0 Multiplexed Address and Data Mode 1 Non Multiplexed Address and Data Mode utilizes optional UHPI_HA 15 0 pins Host data bus is 32 bits in...

Page 61: ...d mode and in Multiplexed Address and Data mode when PAGEM 1 Sets bits 31 24 of the DSP internal address as accessed through UHPI 31 8 Reserved 7 0 HPIAUMB R W 0 LEGEND R W Read Write R Read only n value after reset Figure 4 20 CFGHPIAUMB Register Bit Layout 0x4000 0010 Table 4 14 CFGHPIAUMB Register Bit Field Description 0x4000 0010 RESET READ BIT NO NAME DESCRIPTION VALUE WRITE 31 8 Reserved N A...

Page 62: ...HPI_HAS falling edge 5 ns 12 th HASL HAD Hold time HAD valid after UHPI_HAS falling edge 5 ns 13 tw DSL Pulse duration DS low 15 ns 14 tw DSH Pulse duration DS high 2P ns 15 tsu HAD DSL Setup time HAD valid before DS falling edge 5 ns 16 th DSL HAD Hold time HAD valid after DS falling edge 5 ns 17 tsu HD DSH Setup time HD valid before DS rising edge 5 ns 18 th DSH HD Hold time HD valid after DS ri...

Page 63: ... 1 HPID read with no 10 2H 20 3 auto increment Delay time DS low to UHPI_HRDY 6 td DSL HRDYL ns Case 2 HPID read with low auto increment and read FIFO 10 2H 20 3 initialy empty 7 td HDV HRDYL Delay time HD valid to UHPI_HRDY low 0 ns Case 1 HPIA write 5 2H 20 3 Delay time DS high to Case 2 HPID read with 34 td DSH HRDYL ns UHPI_HRDY low auto increment and read FIFO 5 2H 20 3 initially empty Delay ...

Page 64: ...data Read Write 37 37 6 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 A Depending on the type of write or read operation HPID or HPIC transitions on UHPI_HRDY may or may not occur Figure 4 21 Non Multiplexed Read Write Timings Peripheral and Electrical Specifications 64 Submit Documentation Feedback ...

Page 65: ...Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 A See Figure 4 14 B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on UHPI_HRDY may or may not occur Figure 4 22 Multiplexed Read Timings Using UHPI_HAS Submit Documentation Feedback Peripheral and Electrical...

Page 66: ... Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 A See Figure 4 14 B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on UHPI_HRDY may or may not occur Figure 4 23 Multiplexed Read Timings With UHPI_HAS Held High Peripheral and Electrical Specifications 66 Submit Documentation Fee...

Page 67: ...ital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 A See Figure 4 14 B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on UHPI_HRDY may or may not occur Figure 4 24 Multiplexed Write Timings With UHPI_HAS Held High Submit Documentation Feedback Peripheral and Electrical Specifi...

Page 68: ...The McASPs DO NOT have dedicated AMUTEINx pins TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 The McASP serial port is specifically designed for multichannel audio applications Its key features are Flexible clock and frame sync generation logic and on chip dividers Up to sixteen transmit or receive data pins and serializers Large...

Page 69: ...X2 share pin AHCLKR0 AHCLKR1 ACLKR0 AFSR0 AHCLKR0 AHCLKR1 share pin McASP1 No AHCLKX1 ACLKX1 AFSX1 ACLKR1 AFSR1 Up to 6 AHCLKR0 AHCLKR1 share pin McASP2 Yes ACLKX2 AFSX2 AHCLKR2 ACLKR2 AFSR2 Up to 2 Full functionality on C6727 On C6726 Only available on the C6727 functions only as DIT since only AHCLKX0 AHCLKX2 is available Not available on the C6722 NOTE The McASPs do not have dedicated AMUTEINx ...

Page 70: ...ffected allows receiver to be reset independently from transmitter 0x4400 0064 0x4500 0064 0x4600 0064 RMASK Receive format unit bit mask register 0x4400 0068 0x4500 0068 0x4600 0068 RFMT Receive bit stream format register 0x4400 006C 0x4500 006C 0x4600 006C AFSRCTL Receive frame sync control register 0x4400 0070 0x4500 0070 0x4600 0070 ACLKRCTL Receive clock control register 0x4400 0074 0x4500 00...

Page 71: ...0148 DITUDRB0 Right channel user data register 0 0x4600 014C DITUDRB1 Right channel user data register 1 0x4600 0150 DITUDRB2 Right channel user data register 2 0x4600 0154 DITUDRB3 Right channel user data register 3 0x4600 0158 DITUDRB4 Right channel user data register 4 0x4600 015C DITUDRB5 Right channel user data register 5 0x4400 0180 0x4500 0180 0x4600 0180 SRCTL0 Serializer control register ...

Page 72: ... XBUF15 1 Transmit buffer register for serializer 15 0x4400 0280 0x4500 0280 0x4600 0280 RBUF0 2 Receive buffer register for serializer 0 0x4400 0284 0x4500 0284 0x4600 0284 RBUF1 2 Receive buffer register for serializer 1 0x4400 0288 0x4500 0288 RBUF2 2 Receive buffer register for serializer 2 0x4400 028C 0x4500 028C RBUF3 2 Receive buffer register for serializer 3 0x4400 0290 0x4500 0290 RBUF4 2...

Page 73: ...0x4000 0018 RESET READ BIT NO NAME DESCRIPTION VALUE WRITE 31 3 Reserved N A N A Reads are indeterminate Only 0s should be written to these bits 2 0 AMUTEIN0 0 R W AMUTEIN0 Selects the source of the input to the McASP0 mute input 000 Select the input to be a constant 0 001 Select the input from AXR0 7 SPI1_CLK 010 Select the input from AXR0 8 AXR1 5 SPI1_SOMI 011 Select the input from AXR0 9 AXR1 ...

Page 74: ...0x4000 001C RESET READ BIT NO NAME DESCRIPTION VALUE WRITE 31 3 Reserved N A N A Reads are indeterminate Only 0s should be written to these bits 2 0 AMUTEIN1 0 R W AMUTEIN1 Selects the source of the input to the McASP1 mute input 000 Select the input to be a constant 0 001 Select the input from AXR0 7 SPI1_CLK 010 Select the input from AXR0 8 AXR1 5 SPI1_SOMI 011 Select the input from AXR0 9 AXR1 ...

Page 75: ... READ BIT NO NAME DESCRIPTION VALUE WRITE 31 3 Reserved N A N A Reads are indeterminate Only 0s should be written to these bits 2 0 AMUTEIN2 0 R W AMUTEIN2 Selects the source of the input to the McASP2 mute input 000 Select the input to be a constant 0 001 Select the input from AXR0 7 SPI1_CLK 010 Select the input from AXR0 8 AXR1 5 SPI1_SOMI 011 Select the input from AXR0 9 AXR1 4 SPI1_SIMO 100 S...

Page 76: ...XC ACKRX ns Setup time AFSX input to ACLKX external input 3 Setup time AFSR input to ACLKR external output 3 Setup time AFSX input to ACLKX external output 3 Hold time AFSR input after ACLKR internal 0 Hold time AFSX input after ACLKX internal 0 Hold time AFSR input after ACLKR external input 3 6 th ACKRX AFRX ns Hold time AFSX input after ACLKX external input 3 Hold time AFSR input after ACLKR ex...

Page 77: ...CLKR internal AFSR output 5 Delay time ACLKX internal AFSX output 5 Delay time ACLKR external input AFSR output 10 Delay time ACLKX external input AFSX output 10 Delay time ACLKR external output AFSR output 10 Delay time ACLKX external output AFSX output 10 13 td ACKRX FRX ns Delay time ACLKR internal AFSR output 1 Delay time ACLKX internal AFSX output 1 Delay time ACLKR external input AFSR output...

Page 78: ...KR X CLKRP CLKXP 1 B TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 A For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and the McASP receiver is configured for falling edge to shift data in B For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McA...

Page 79: ...LKXP 0 B ACLKR X CLKRP CLKXP 1 A TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 A For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McASP receiver is configured for rising edge to shift data in B For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out ...

Page 80: ...ect pin is most useful to enable in slave mode when there are other slave devices on the same SPI port The C672x will only shift data and drive the SPIx_SOMI pin when SPIx_SCS is held low In slave mode SPIx_ENA is an optional output and can be driven in either a push pull or open drain manner The SPIx_ENA output provides the status of the internal transmit buffer SPIDAT0 1 registers In four pin mo...

Page 81: ...Ix_SOMI SPIx_CLK SPIx_CLK SPIx_ENA SPIx_ENA SPIx_SCS SPIx_SCS TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 32 Illustration of SPI Master to SPI Slave Connection Submit Documentation Feedback Peripheral and Electrical Specifications 81 ...

Page 82: ...4 SPIPC4 Pin Control Register 4 Pin Data Set 0x4700 0028 0x4800 0028 SPIPC5 Pin Control Register 5 Pin Data Clear 0x4700 002C 0x4800 002C Reserved Reserved Do not write to this register 0x4700 0030 0x4800 0030 Reserved Reserved Do not write to this register 0x4700 0034 0x4800 0034 Reserved Reserved Do not write to this register 0x4700 0038 0x4800 0038 SPIDAT0 Shift Register 0 without format select...

Page 83: ...ng Polarity 1 Phase 1 15 from SPIx_CLK rising Polarity 0 Phase 0 0 5tc SPC M 10 from SPIx_CLK falling Polarity 0 Phase 1 Output hold time 0 5tc SPC M 10 from SPIx_CLK rising SPIx_SIMO valid after 6 toh SPC_SIMO M ns receive edge of SPIxCLK Polarity 1 Phase 0 0 5tc SPC M 10 except for final bit 3 from SPIx_CLK rising Polarity 1 Phase 1 0 5tc SPC M 10 from SPIx_CLK falling Polarity 0 Phase 0 0 5P 15...

Page 84: ...Polarity 1 Phase 0 0 5tc SPC S 10 except for final bit 4 from SPIx_CLK rising Polarity 1 Phase 1 0 5tc SPC S 10 from SPIx_CLK falling Polarity 0 Phase 0 0 5P 15 to SPIx_CLK falling Polarity 0 Phase 1 0 5P 15 Input Setup Time to SPIx_CLK rising 15 tsu SIMO_SPC S SPIx_SIMO valid before ns Polarity 1 Phase 0 receive edge of SPIx_CLK 0 5P 15 to SPIx_CLK rising Polarity 1 Phase 1 0 5P 15 to SPIx_CLK fa...

Page 85: ...ith new data before SPIx_ENA deassertion Table 4 28 Additional 1 SPI Master Timings 4 Pin Chip Select Option 2 3 NO MIN MAX UNIT Polarity 0 Phase 0 2P 10 to SPIx_CLK rising Polarity 0 Phase 1 0 5tc SPC M 2P 10 to SPIx_CLK rising Delay from SPIx_SCS active to 19 td SCS_SPC M ns first SPIx_CLK 4 5 Polarity 1 Phase 0 2P 10 to SPIx_CLK falling Polarity 1 Phase 1 0 5tc SPC M 2P 10 to SPIx_CLK falling P...

Page 86: ...Ix_CLK 7 8 9 2P 10 to SPIx_CLK falling Polarity 1 Phase 1 0 5tc SPC M 2P 10 to SPIx_CLK falling Polarity 0 Phase 0 3P 15 to SPIx_CLK rising Polarity 0 Phase 1 0 5tc SPC M 3P 15 Delay from assertion of to SPIx_CLK rising 23 td ENA_SPC M SPIx_ENA low to first ns Polarity 1 Phase 0 SPIx_CLK edge 10 3P 15 to SPIx_CLK falling Polarity 1 Phase 1 0 5tc SPC M 3P 15 to SPIx_CLK falling 1 These parameters a...

Page 87: ...le 4 31 Additional 1 SPI Slave Timings 4 Pin Chip Select Option 2 3 NO MIN MAX UNIT Required delay from SPIx_SCS asserted at slave to first 25 td SCSL_SPC S P ns SPIx_CLK edge at slave Polarity 0 Phase 0 0 5tc SPC M P 10 from SPIx_CLK falling Polarity 0 Phase 1 P 10 Required delay from final from SPIx_CLK falling 26 td SPC_SCSH S SPIx_CLK edge before ns Polarity 1 Phase 0 SPIx_SCS is deasserted 0 ...

Page 88: ...Delay from master deasserting SPIx_SCS to slave driving 29 tena SCSL_ENA S 15 ns SPIx_ENA valid Polarity 0 Phase 0 2P 15 from SPIx_CLK falling Polarity 0 Phase 1 Delay from final clock receive 2P 15 from SPIx_CLK rising edge on SPIx_CLK to slave 30 tdis SPC_ENA S ns 3 stating or driving high Polarity 1 Phase 0 2P 15 SPIx_ENA 4 from SPIx_CLK rising Polarity 1 Phase 1 2P 15 from SPIx_CLK falling 1 T...

Page 89: ...1 MI n MO 0 MO 1 MO n 1 MO n MI 0 MI 1 MI n 1 MI n 6 6 7 7 7 7 8 8 8 8 3 2 6 1 4 4 4 4 5 5 5 6 MASTER MODE POLARITY 0 PHASE 0 MASTER MODE POLARITY 0 PHASE 1 MASTER MODE POLARITY 1 PHASE 0 MASTER MODE POLARITY 1 PHASE 1 5 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 33 SPI Timings Master Mode Submit Documentation Feedba...

Page 90: ... 0 SI 1 SI n 1 SI n SO 0 SO 1 SO n 1 SO n 14 14 15 15 15 15 16 16 16 16 11 10 14 9 12 12 12 12 13 13 13 13 14 SLAVE MODE POLARITY 0 PHASE 0 SLAVE MODE POLARITY 0 PHASE 1 SLAVE MODE POLARITY 1 PHASE 0 SLAVE MODE POLARITY 1 PHASE 1 TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 34 SPI Timings Slave Mode Peripheral and Elec...

Page 91: ...MO 0 MO 1 MO n 1 MO n MI 0 MI 1 MI n 1 MI n 17 19 21 22 23 20 18 20 18 MASTER MODE 4 PIN WITH ENABLE MASTER MODE 5 PIN A DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3 STATE REQUIRES EXTERNAL PULLUP DESEL A DESEL A TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 35 SPI Timings Master Mode 4 Pin and 5 Pin Submit Documentation...

Page 92: ...I n 1 SI n 24 26 28 26 30 28 25 25 27 29 SLAVE MODE 4 PIN WITH ENABLE SLAVE MODE 4 PIN WITH CHIP SELECT SLAVE MODE 5 PIN DESEL A DESEL A A DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3 STATE REQUIRES EXTERNAL PULLUP TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 4 36 SPI Timings Slave Mode 4 Pin and 5 Pin 92 Peripheral and E...

Page 93: ...2CPDCLR Pin Data Clear Register Interrupt DMA Requests TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Having two I2C modules on the C672x simplifies system architecture since one module may be used by the DSP to control local peripherals ICs DACs ADCs etc while the other may be used to communicate with other controllers in a syst...

Page 94: ...2CDRR Data Receive Register 0x4900 001C 0x4A00 001C I2CSAR Slave Address Register 0x4900 0020 0x4A00 0020 I2CDXR Data Transmit Register 0x4900 0024 0x4A00 0024 I2CMDR Mode Register 0x4900 0028 0x4A00 0028 I2CISR Interrupt Source Register 0x4900 002C 0x4A00 002C I2CEMDR Extended Mode Register 0x4900 0030 0x4A00 0030 I2CPSC Prescale Register 0x4900 0034 0x4A00 0034 I2CPID1 Peripheral Identification ...

Page 95: ...2Cx_SCL low µs Fast Mode 0 0 9 Standard Mode 4 7 8 tw SDAH Pulse duration I2Cx_SDA high µs Fast Mode 1 3 Standard Mode 1000 9 tr SDA Rise time I2Cx_SDA ns Fast Mode 20 0 1Cb 300 Standard Mode 1000 10 tr SCL Rise time I2Cx_SCL ns Fast Mode 20 0 1Cb 300 Standard Mode 300 11 tf SDA Fall time I2Cx_SDA ns Fast Mode 20 0 1Cb 300 Standard Mode 300 12 tf SCL Fall time I2Cx_SCL ns Fast Mode 20 0 1Cb 300 St...

Page 96: ...ard Mode 4 20 tw SCLH Pulse duration I2Cx_SCL high µs Fast Mode 0 6 Standard Mode 250 Setup time I2Cx_SDA valid before I2Cx_SCL 21 tsu SDAV SCLH ns high Fast Mode 100 Standard Mode 0 22 th SCLL SDAV Hold time I2Cx_SDA valid after I2Cx_SCL low µs Fast Mode 0 0 9 Standard Mode 4 7 23 tw SDAH Pulse duration I2Cx_SDA high µs Fast Mode 1 3 Standard Mode 4 Setup time I2Cx_SCL high before I2Cx_SDA 28 tsu...

Page 97: ... of the RTI module Figure 4 40 RTI Timer Block Diagram The RTI timer module consists of two independent counters which are both clocked from SYSCLK2 but may be started individually and may have different prescaler settings The counters provide the timebase against which four output comparators operate These comparators may be programmed to generate periodic interrupts The comparators include an ad...

Page 98: ...pare value compared with prescale counter 0 0x4200 0020 RTICAFRC0 Capture Free Running Counter 0 Current value of free running counter 0 on external event 0x4200 0024 RTICAUC0 Capture Up Counter 0 Current value of prescale counter 0 on external event 0x4200 0030 RTIFRC1 Free Running Counter 1 Current value of free running counter 1 0x4200 0034 RTIUC1 Up Counter 1 Current value of prescale counter ...

Page 99: ...s a description of the bits 31 8 Reserved 7 6 4 3 2 0 Reserved CAPSEL1 Reserved CAPSEL0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 4 41 CFGRTI Register Bit Layout 0x4000 0014 Table 4 37 CFGRTI Register Bit Field Description 0x4000 0014 RESET READ BIT NO NAME DESCRIPTION VALUE WRITE 31 7 3 Reserved N A N A Reads are indeterminate Only 0s should be written to these bits...

Page 100: ... V LVCMOS compatible clock input with the CLKIN pin Note that the two clock inputs are logically combined internally before the PLL so the clock input that is not used must be tied to ground Figure 4 42 C672x Clock Input Options If the on chip oscillator is chosen then the recommended component values for Figure 4 42 a are listed in Table 4 38 Table 4 38 Recommended On Chip Oscillator Components F...

Page 101: ...s Table 4 39 CLKIN Timing Requirements NO MIN MAX UNIT 1 fosc Oscillator frequency range OSCIN OSCOUT 12 25 MHz 2 tc CLKIN Cycle time external clock driven on CLKIN 20 ns 3 tw CLKINH Pulse width CLKIN high 0 4tc CLKIN ns 4 tw CLKINL Pulse width CLKIN low 0 4tc CLKIN ns 5 tt CLKIN Transition time CLKIN 5 ns 6 fPLL Frequency range of PLL input 12 50 MHz Submit Documentation Feedback Peripheral and E...

Page 102: ... The C672x DSP generates the high frequency internal clocks it requires through an on chip PLL The input to the PLL is either from the on chip oscillator OSCIN pin or from an external clock on the CLKIN pin The PLL outputs four clocks that have programmable divider options Figure 4 43 illustrates the PLL Topology The PLL is disabled by default after a device reset It must be configured by software...

Page 103: ... 2 3 or 4 of SYSCLK1 8 SYSCLK3 frequency set by PLLM and dividers D0 D3 PLLOUT 3 EMIF Frequency Specification 1 Some values for the D0 divider produce results outside of this range and should not be selected 2 In general selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter CAUTION SYSCLK1 SYSCLK2 SYSCLK3 must be configured as aligned by setting ALNCTL 2 0...

Page 104: ...cation register 0x4100 0100 PLLCSR PLL control status register 0x4100 0110 PLLM PLL multiplier control register 0x4100 0114 PLLDIV0 PLL controller divider register 0 0x4100 0118 PLLDIV1 PLL controller divider register 1 0x4100 011C PLLDIV2 PLL controller divider register 2 0x4100 0120 PLLDIV3 PLL controller divider register 3 0x4100 0138 PLLCMD PLL controller command register 0x4100 013C PLLSTAT P...

Page 105: ...t Digital Out High Speed Parallel Data DSP Control SPI or I2C 6 Independent Audio Zones 3 TX 3 RX 16 Serial Data Pins TMS320C6727 TMS320C6726 TMS320C6722 Floating Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 Figure 5 1 illustrates a high level block diagram of the device and other devices to which it may typically connect See Section 1 2 for an overview of each major bloc...

Page 106: ...de to the SPRS268D device specific data sheet to make it an SPRS268E revision Scope Corrected addresses of the XGBLCTL register in Table 4 18 McASP Registers Accessed Through Peripheral Configuration Bus ADDS CHANGES DELETES Table 4 18 McASP Registers Accessed Through Peripheral Configuration Bus Corrected addresses of XGBLCTL Transmitter Global Control Register Revision History 106 Submit Documen...

Page 107: ...ARRAY Two Signal Two Plane 76 2 x 76 2 mm PCB 1 2 3 1 RθJA Thermal Resistance Junction to Ambient 10 6 x 10 6 mm 10 6 x 10 6 mm 6 x 6 20 0 7 5 x 7 5 mm 7 5 x 7 5 mm 5 x 5 22 0 2 ΨJP Thermal Metric Junction to Power Pad 10 6 x 10 6 mm 10 6 x 10 6 mm 6 x 6 0 39 0 Double Sided 76 2 x 76 2 mm PCB 1 2 4 3 RθJA Thermal Resistance Junction to Ambient 10 6 x 10 6 mm 10 6 x 10 6 mm 6 x 6 49 0 10 6 x 10 6 m...

Page 108: ... specification for this device between 0 050 mm and 0 150 mm is measured from the seating plane established by the three lowest package pins to the lowest point on the package body Due to warpage the lowest point on the package body is located in the center of the package at the exposed thermal pad Using this definition of standoff height provides the correct result for determining the correct sol...

Page 109: ...rint for this device In general for proper thermal performance the thermal pad under the package body should be as large as possible However the soldermask opening for the PowerPAD should be sized to match the pad size on the 144 pin RFP package as illustrated in Figure 7 2 Figure 7 2 Soldermask Opening Should Match Size of DSP Thermal Pad The following packaging information reflects the most curr...

Page 110: ......

Page 111: ... Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free...

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Page 114: ...ice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertis...

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