8.5 Sequential Sampling Mode
The default behavior of the ADC is to treat triggered SOCs as single conversions to be processed sequentially.
Sequential sampling can convert both A-channels and B-channels without restriction on ordering.
However, a by-product of supporting the Simultaneous Sampling Mode is that the sampling capacitor from the
paired simultaneous channel will also be connected to its respective input at the same time as the desired
sequential sampling ACQPS window; the ADC will not convert the sample from the paired channel. (The
Simultaneous Sampling Mode is described in
, and the sampling capacitor is denoted as Ch in
For example, assume that SOC0 is configured to convert ADCINB3, and SOC1 is configured to convert
ADCINA5. If SOC0 and SOC1 are triggered together, the following sequence of simplified events would take
place:
1. SOC0 Sample: A-channel and B-channel sampling capacitors are connected to ADCINA3 and ADCINB3 for
SOC0 ACQPS window
2. SOC0 Convert: ADC converts B-channel sampling capacitor and stores result to ADCRESULT0
3. SOC1 Sample: A-channel and B-channel sampling capacitors are connected to ADCINA5 and ADCINB5 for
SOC1 ACQPS window
4. SOC1 Convert: ADC converts A-channel sampling capacitor and stores result to ADCRESULT1
The extraneous sampling capacitor exposure should be taken into consideration for input signals that have a
slow recovery or settling time. Typical examples of slow inputs are sensors with high impedance outputs and
signals that are conditioned with low-pass filters.
8.6 Simultaneous Sampling Mode
In some applications it is important to keep the delay between the sampling of two signals minimal. The
ADC contains dual sample and hold circuits to allow two different channels to be sampled simultaneously.
Simultaneous sampling mode is configured for a pair of SOCx's with the ADCSAMPLEMODE register. The
even-numbered SOCx and the following odd-numbered SOCx (SOC0 and SOC1) are coupled together with one
enable bit (SIMULEN0, in this case). The coupling behavior is as follows:
• Either SOCx’s trigger will start a pair of conversions.
• The pair of channels converted will consist of the A-channel and the B-channel corresponding to the value of
the CHSEL field of the triggered SOCx. The valid values in this mode are 0-7.
• Both channels will be sampled simultaneously.
• The A channel will always convert first.
• The even EOCx pulse will be generated based off of the A-channel conversion, the odd EOCx pulse will be
generated off of the B-channel conversion. See
for an explanation of the EOCx signals.
• The result of the A-channel conversion is placed in the even ADCRESULTx register and the result of the
B-channel conversion is written to the odd ADCRESULTx register.
For example, if the ADCSAMPLEMODE.SIMULEN0 bit is set, and SOC0 is configured as follows:
• CHSEL = 2 (ADCINA2/ADCINB2 pair)
• TRIGSEL = 5 (ADCTRIG5 = ePWM1.ADCSOCA)
When the ePWM1 sends out an ADCSOCA trigger, both ADCINA2 and ADCINB2 will be sampled
simultaneously (assuming priority). Immediately after, the ADCINA2 channel will be converted and its value
will be stored in the ADCRESULT0 register. Depending on the ADCCTL1.INTPULSEPOS setting, the
EOC0 pulse will either occur when the conversion of ADCINA2 begins or completes. Then the ADCINB2
channel will be converted and its value will be stored in the ADCRESULT1 register. Depending on the
ADCCTL1.INTPULSEPOS setting, the EOC1 pulse will either occur when the conversion of ADCINB2 begins or
completes.
Typically in an application it is expected that only the even SOCx of the pair will be used. However, it is possible
to use the odd SOCx instead, or even both. In the latter case, both SOCx triggers will start a conversion.
Therefore, caution is urged as both SOCx's will store their results to the same ADCRESULTx registers, possibly
overwriting each other.
Analog-to-Digital Converter (ADC)
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
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Summary of Contents for TMS320 2806 Series
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