Texas Instruments TMS320 2806 Series, Technical Reference Manual

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The CPU then prepares to service the interrupt. This preparation process is described in detail in TMS320C28x
DSP CPU and Instruction Set Reference Guide . In preparation, the corresponding CPU IFR and IER bits are
cleared, EALLOW and LOOP are cleared, INTM and DBGM are set, the pipeline is flushed and the return
address is stored, and the automatic context save is performed. The vector of the ISR is then fetched from the
PIE module. If the interrupt request comes from a multiplexed interrupt, the PIE module uses the group PIEIERx
and PIEIFRx registers to decode which interrupt needs to be serviced. This decode process is described in
Section 1.6.3.3 .
The address for the interrupt service routine that is executed is fetched directly from the PIE interrupt vector
table. There is one 32-bit vector for each of the possible 96 interrupts within the PIE. Interrupt flags within the
PIE module (PIEIFRx.y) are automatically cleared when the interrupt vector is fetched. The PIE acknowledge bit
for a given interrupt group, however, must be cleared manually when ready to receive more interrupts from the
PIE group.
1.6.2 Vector Table Mapping
On 28xx devices, the interrupt vector table can be mapped to four distinct locations in memory. In practice only
the PIE vector table mapping is used.
This vector mapping is controlled by the following mode bits/signals:
VMAP: VMAP is found in the Status Register 1 ST1 (bit 3). A device reset sets this bit to 1. The state of this bit can be modified
by writing to ST1 or by SETC/CLRC VMAP instructions. For normal operation leave this bit set.
M0M1MAP: M0M1MAP is found in the Status Register 1 ST1 (bit 11). A device reset sets this bit to 1. The state of this bit can be
modified by writing to ST1 or by SETC/CLRC M0M1MAP instructions. For normal 28xx device operation, this bit should
remain set. M0M1MAP = 0 is reserved for TI testing only.
ENPIE: ENPIE is found in the PIECTRL Register (bit 0). The default value of this bit, on reset, is set to 0 (PIE disabled). The
state of this bit can be modified after reset by writing to the PIECTRL register (address 0x0000 0CE0).
Using these bits and signals the possible vector table mappings are shown in Table 1-117 .
Table 1-117. Interrupt Vector Table Mapping
Vector MAPS Vectors Fetched From Address Range VMAP M0M1MAP ENPIE
M1 Vector
(1)
M1 SARAM Block 0x000000 - 0x00003F 0 0 X
M0 Vector
(1)
M0 SARAM Block 0x000000 - 0x00003F 0 1 X
BROM Vector Boot ROM Block 0x3FFFC0 - 0x3FFFFF 1 X 0
PIE Vector PIE Block 0x000D00 - 0x000DFF 1 X 1
(1) Vector map M0 and M1 Vector is a reserved mode only. On the 28x devices these are used as SARAM.
The M1 and M0 vector table mapping are reserved for TI testing only. When using other vector mappings, the
M0 and M1 memory blocks are treated as SARAM blocks and can be used freely without any restrictions.
After a device reset operation, the vector table is mapped as shown in Table 1-118 .
Table 1-118. Vector Table Mapping After Reset Operation
Vector MAPS Reset Fetched From Address Range VMAP
(1)
M0M1MAP
(1)
ENPIE
(1)
BROM Vector
(2)
Boot ROM Block 0x3FFFC0 - 0x3FFFFF 1 1 0
(1) On the 28x devices, the VMAP and M0M1MAP modes are set to 1 on reset. The ENPIE mode is forced to 0 on reset.
(2) The reset vector is always fetched from the boot ROM.
After the reset and boot is complete, the PIE vector table should be initialized by the user's code. Then the
application enables the PIE vector table. From that point on the interrupt vectors are fetched from the PIE vector
table. Note: when a reset occurs, the reset vector is always fetched from the vector table as shown in
Table
1-118 . After a reset the PIE vector table is always disabled.
Figure 1-95 illustrates the process by which the vector table mapping is selected.
System Control and Interrupts www.ti.com
170 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
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