TMP A
TMP B
TMP C
TMP D
TMP E
TMP F
TMP G
TMP H
I C Interface
and V
2
DUT
10-Pin Connector
Socket
T
est P
oint
Headers
U1
TP1-4
Theory of Operation
www.ti.com
4
SBOU099A – January 2011 – Revised April 2018
Submit Documentation Feedback
Copyright © 2011–2018, Texas Instruments Incorporated
TMP103EVM
3
Theory of Operation
The TMP103EVM is very modest in its design, and only requires the two-wire I
2
C lines (SDA and SCLK)
and V
DUT
/GND to supply a constant 3.3 V and power return, as shown in
Figure 3
. The TMP103EVM also
has several test points to monitor these signal lines, and ground, in case users may want to use their own
signals or verify I
2
C communications.
Figure 3. TMP103 Test Board Block Diagram
3.1
Signal Definitions of H1 (10-Pin Male Connector Socket)
Table 3
shows the pinout for the 10-pin connector socket used to communicate between the TMP103EVM
and the SM-USB-DIG. It should be noted that the TMP103EVM only uses the necessary I
2
C
communication lines (Pins 1 and 3) and the V
DUT
and GND (Pins 6 and 8) pins to issue commands to the
TMP103 sensors.
(1)
When V
DUT
is Hi-Z, all digital I/Os are Hi-Z as well.
Table 3. Pin Connector
Pin on U1
Signal
Description
1
I2C_SCL
I
2
C clock signal (SCL)
2
CTRL/MEAS4
GPIO: Control output or measure
input
3
I2C_SDA1
I
2
C data signal (SDA)
4
CTRL/MEAS5
GPIO: Control output or measure
input
5
SPI_DOUT1
SPI data output (MOSI)
6
V
DUT
Switchable DUT power supply:
+3.3 V, +5 V, Hi-Z
(disconnected).
(1)
7
SPI_CLK
SPI clock signal (SCLK)
8
GND
Power return (GND)
9
SPI_CS1
SPI chip select Signal (CS)
10
SPI_DIN1
SPI data input (MISO)
