Texas Instruments TM4C1294NCPDT, Datasheet

Page: 899 / 1890

Register 17: EPI Status (EPISTAT), offset 0x060
This register indicates which non-blocking read register is currently active; it also indicates whether
the external interface is busy performing a write or non-blocking read (it cannot be performing a
blocking read, as the bus would be blocked and as a result, this register could not be accessed).
This register is useful to determining which non-blocking read register is active when both are loaded
with values and when implementing sequencing or sharing.
This register is also useful when canceling non-blocking reads, as it shows how many values were
read by the canceled side.
EPI Status (EPISTAT)
Base 0x400D.0000
Offset 0x060
Type RO, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ACTIVE reserved NBRBUSY WBUSY INITSEQ XFEMPTY XFFULL reserved
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0x0000.00 RO reserved 31:9
External FIFO Full
This bit provides information on the XFIFO when in the FIFO sub-mode
of the Host Bus n mode with the
XFFEN
bit set in the EPIHBnCFG
register. The
EPI0S26
signal reflects the status of this bit.
Description Value
The external device is not gating the clock. 0
The XFIFO is signaling as full (the FIFO full signal is high).
Attempts to write in this case are stalled until the XFIFO full
signal goes low or the counter times out as specified by the
MAXWAIT
field.
1
0 RO XFFULL 8
External FIFO Empty
This bit provides information on the XFIFO when in the FIFO sub-mode
of the Host Bus n mode with the
XFEEN
bit set in the EPIHBnCFG
register. The
EPI0S27
signal reflects the status of this bit.
Description Value
The external device is not gating the clock. 0
The XFIFO is signaling as empty (the FIFO empty signal is
high).
Attempts to read in this case are stalled until the XFIFO empty
signal goes low or the counter times out as specified by the
MAXWAIT
field.
1
0 RO XFEMPTY 7
899 June 18, 2014
Texas Instruments-Production Data
Tiva
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TM4C1294NCPDT Microcontroller