Texas Instruments TM4C1294NCPDT, Datasheet

Page: 854 / 1890

Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1
Clock
(
EPI0S31
)
WR
(
EPI0S28
)
Address
Data
11.5 Register Map
Table 11-13 on page 854 lists the EPI registers. The offset listed is a hexadecimal increment to the
register's address, relative to the base address of 0x400D.0000. Note that the EPI controller clock
must be enabled before the registers can be programmed (see page 386). There must be a delay
of 3 system clocks after the EPI module clock is enabled before any EPI module registers are
accessed.
Note: A write immediately followed by a read of the same register, may not return correct data. A
delay (instruction or NOP) must be inserted between the write and the read for correct
operation. Read-write does not have this issue, so use of read-write for clear of error interrupt
cause is not affected.
Note: For all versions of EPI, only WORD read and write accesses to registers are supported.
Table 11-13. External Peripheral Interface (EPI) Register Map
See
page
Description Reset Type Name Offset
857 EPI Configuration 0x0000.0000 RW EPICFG 0x000
859 EPI Main Baud Rate 0x0000.0000 RW EPIBAUD 0x004
861 EPI Main Baud Rate 0x0000.0000 RW EPIBAUD2 0x008
863 EPI SDRAM Configuration 0x82EE.0000 RW EPISDRAMCFG 0x010
865 EPI Host-Bus 8 Configuration 0x0008.FF00 RW EPIHB8CFG 0x010
870 EPI Host-Bus 16 Configuration 0x0008.FF00 RW EPIHB16CFG 0x010
876 EPI General-Purpose Configuration 0x0000.0000 RW EPIGPCFG 0x010
879 EPI Host-Bus 8 Configuration 2 0x0008.0000 RW EPIHB8CFG2 0x014
885 EPI Host-Bus 16 Configuration 2 0x0008.0000 RW EPIHB16CFG2 0x014
892 EPI Address Map 0x0000.0000 RW EPIADDRMAP 0x01C
895 EPI Read Size 0 0x0000.0003 RW EPIRSIZE0 0x020
896 EPI Read Address 0 0x0000.0000 RW EPIRADDR0 0x024
897 EPI Non-Blocking Read Data 0 0x0000.0000 RW EPIRPSTD0 0x028
895 EPI Read Size 1 0x0000.0003 RW EPIRSIZE1 0x030
June 18, 2014 854
Texas Instruments-Production Data
External Peripheral Interface (EPI)