Texas Instruments TM4C1294NCPDT, Datasheet

Page: 896 / 1890

Register 13: EPI Read Address 0 (EPIRADDR0), offset 0x024
Register 14: EPI Read Address 1 (EPIRADDR1), offset 0x034
This register holds the current address value. When performing non-blocking reads via the
EPIRPSTDn registers, this register's value forms the address (when used by the mode). That is,
when an EPIRPSTDn register is written with a non-0 value, this register is used as the first address.
After each read, it is incremented by the size specified by the corresponding EPIRSIZEn register.
Thus at the end of a read, this register contains the next address for the next read. For example, if
the last read was 0x20, and the size is word, then the register contains 0x24. When a non-blocking
read is cancelled, this register contains the next address that would have been read had it not been
cancelled. For example, if reading by bytes and 0x103 had been read but not 0x104, this register
contains 0x104. In this manner, the system can determine the number of values in the NBRFIFO
to drain.
Note that changing this register while a read is active has an unpredictable effect due to race
condition.
EPI Read Address n (EPIRADDRn)
Base 0x400D.0000
Offset 0x024
Type RW, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADDR
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Current Address
Next address to read.
0x0000.0000 RW ADDR 31:0
June 18, 2014 896
Texas Instruments-Production Data
External Peripheral Interface (EPI)