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The recommended maximum delay capacitor for the TLV841C is limited to 10 µF as this ensures there is enough 
time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the 
previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before 
the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and 
the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the capacitor has 
enough time to fully discharge during the duration of the voltage fault.

The TLV841EVM provides jumper J6 to configure the CT pin and test point TP3 to monitor the CT pin. Place a 
shunt jumper on pin 1 (left pin) and pin 2 (middle pin) of jumper J6 to connect CT to delay capacitor C2. This 
connects the CT pin to a 0.01 µF capacitor to set the RESET delay (t

D

) to ~6.2 ms. Place a shunt between pin 

2 (middle pin) and pin 3 (right pin) of jumper J6 to connect CT to delay capacitor C3. This connects the CT pin 
to a 0.1 µF capacitor to set the RESET delay (t

D

) to ~61.9 ms. By removing the shunt jumper from jumper J6, 

the RESET time delay defaults to the minimum value of 80 µs or less. If using a different delay capacitor, the 
capacitor must be ≥ 100 pF to be recognized.

For the TLV841M / TLV841S variant or TLV841C where C

T

 is floating, 

Figure 4-3

 shows the typical reset delay 

time. Depending on how much VDD deviates from the specified threshold, the typical reset delay value (~40 µs) 
may be shorter or longer.

Reset Delay (t

D

) = 46.8 

s

VDD

RESET

Figure 4-3. TLV841EVM RESET Delay Time (t

D

) for TLV841S/M or for TLV841C where C

T

 Pin Is Floating 

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (January 2021) to Revision A (June 2021)

Page

• Updated supply voltage from 6 V to 5.5 V..........................................................................................................

2

• Updated schematic.............................................................................................................................................

5

• Included supply voltage range for TLV841C and TLV841M with open-drain and push-pull outputs.................

11

Revision History

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14

TLV841EVM Voltage Supervisor User Guide

SNVU755A – JANUARY 2021 – REVISED JUNE 2021

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Summary of Contents for TLV841EVM

Page 1: ...Program tD via CT TLV841C 13 5 Revision History 14 List of Figures Figure 1 1 TLV841EVM Board Top 2 Figure 1 2 TLV841EVM Board Bottom 3 Figure 2 1 TLV841EVM Schematic with TLV841S 5 Figure 2 2 Compone...

Page 2: ...t use a pull up resistor Therefore R1 on the TLV841EVM must be disconnected Please also note if using TLV841EVM with the active high variant TLV841xxPHxx the active low RESET label on the EVM board an...

Page 3: ...LV841 1 2 TLV841 Applications Personal electronics Home theater and entertainment Electronic point of sale Grid infrastructure Data center and enterprise computing www ti com Introduction SNVU755A JAN...

Page 4: ...description of the TLV841EVM schematic bill of materials BOM and layout Schematic Bill of Materials and Layout www ti com 4 TLV841EVM Voltage Supervisor User Guide SNVU755A JANUARY 2021 REVISED JUNE 2...

Page 5: ...TLV841EVM Schematic with TLV841S www ti com Schematic Bill of Materials and Layout SNVU755A JANUARY 2021 REVISED JUNE 2021 Submit Document Feedback TLV841EVM Voltage Supervisor User Guide 5 Copyright...

Page 6: ...0 1 W 0603 0603 RC0603FR 0730K1L Yageo America R2 1 47 5k RES 47 5 k 1 0 1 W 0603 0603 RC0603FR 0747K5L Yageo America R3 1 10k RES 10 0 k 1 0 1 W 0603 0603 RC0603FR 0710KL Yageo America SH J1 SH J2 S...

Page 7: ...Figure 2 7 show the top and bottom layers and Figure 2 8 shows the top solder mask of the EVM 2 4 Layout Figure 2 2 Component Placement Top Assembly Figure 2 3 Component Placement Bottom Assembly Figu...

Page 8: ...m Layer Figure 2 8 Top Solder Mask Schematic Bill of Materials and Layout www ti com 8 TLV841EVM Voltage Supervisor User Guide SNVU755A JANUARY 2021 REVISED JUNE 2021 Submit Document Feedback Copyrigh...

Page 9: ...upply TP2 RESET Connection to RESET pin Allows the user to monitor the RESET output pin TP3 MR SENSE CT Connect to SENSE pin variant option 1 Connect to MR pin variant option 2 Connect to CT pin varia...

Page 10: ...capacitor to reduce the sensitivity of transient voltages on the monitored signal Connecting C2 to the SENSE input will affect the timing specs such as reset time delay tD Pin 2 CT to Pin 3 C3 For TLV...

Page 11: ...BHR See Table 4 1 for information on the default EVM threshold voltage values OPTIONAL Although not required in most cases for noisy applications the TLV841EVM contains jumper J6 Jumper J6 is meant fo...

Page 12: ...gic high due to the internal pull up resistor and RESET is de asserted to a logic high after the user defined delay expires If jumper J8 is left floating the device operates normally as the MR pin def...

Page 13: ...Delay Programming Program tD via CT TLV841C The TLV841C device variant has two options for setting the RESET time delay connect CT pin to a capacitor to GND or leave CT pin floating The reset time del...

Page 14: ...onnect CT to delay capacitor C3 This connects the CT pin to a 0 1 F capacitor to set the RESET delay tD to 61 9 ms By removing the shunt jumper from jumper J6 the RESET time delay defaults to the mini...

Page 15: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 16: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 17: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 18: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 19: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 20: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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