4 EVM Setup and Operation
This section describes the functionality and operation of the TLV841EVM. The user must read the
datasheet for electrical characteristics of the device.
4.1 Input Power (V
DD
)
The VDD supply is connected through the J2 header on board. Both pins of jumper J2 are connected together
where power can be applied to either pin. The TLV841S voltage range is 0.85 V to 5.5 V whereas the TLV841C
and TLV841M has a voltage range of 0.7 V to 5.5 V for the open-drain (DL) and push-pull (PL) active-low
variants. For all push-pull active-high (PH) variants, the voltage range is 1 V to 5.5 V.
4.2 Monitoring Voltage on SENSE Pin (TLV841S)
The TLV841S device variant option monitors the voltage via the SENSE pin. The user can connect to the
SENSE pin using TP3. The TLV841EVM provides two options for voltage monitoring.
1. Monitor VDD: VDD can be monitored by connecting the shunt to jumper J4 which creates a short and makes
V
mon
= VDD
2. Voltage divider for V
mon
: V
mon
connects to the SENSE pin through a voltage divider. To use this voltage
divider, connect the shunt to jumper J8 (pin 3 [Rdiv] to pin 2 [GND]). This voltage divider can be adjusted to
monitor any voltage above the V
IT-
, which is 0.505 V, for the default device
TL841SADL01YBHR
.
(See
for information on the default EVM threshold voltage values.)
OPTIONAL:
Although not required in most cases, for noisy applications, the TLV841EVM contains jumper J6
(Jumper J6 is meant for TLV841C option) that allows the user the flexibility to add a bypass capacitor C2 or C3
on the SENSE input. Adding a bypass capacitor at the SENSE input will help reduce the sensitivity to transient
voltages on the monitored signal but affect the timing specs such as increasing the reset time delay t
D
.
Table 4-1. Nominal Input Threshold Voltage
DEVICE
V
IT-
V
IT+
V
mon
NEGATIVE-GOING
THRESHOLD VOLTAGE
V
mon
POSITIVE-GOING
THRESHOLD VOLTAGE
TLV841SADL01,
R1 = 47.5 kΩ, R2 = 10 kΩ
(x0.174 Voltage Divider Ratio)
0.505 V
0.530 V
2.90 V
3.05 V
Upon start-up, the TLV841 requires VDD to be above V
POR
= 0.7 V before the RESET output is in the correct
logic state. The TLV841 has built-in glitch immunity so voltage transients on VDD or SENSE are ignored if
the pulse duration is 10 µs or less as shown in
. The glitch immunity specification depends on the
amplitude of the voltage transient and the operating conditions. Please see the Glitch Immunity specification in
the Timing Requirements section of the
datasheet for more detailed information.
EVM Setup and Operation
SNVU755A – JANUARY 2021 – REVISED JUNE 2021
TLV841EVM Voltage Supervisor User Guide
11
Copyright © 2021 Texas Instruments Incorporated
