The reset signal will be asserted low when:
• The voltage on the SENSE pin falls below V
IT-
for the TLV841S version. See
• The MR pin is pulled low or when the voltage on the VDD pin falls below V
IT-
for the TLV841M version
• The voltage on the VDD pin falls below V
IT-
for the TLV841C version.
• For TLV841M and TLV841C device variant option, the propagation detect delay t
P_HL
when VDD goes below
V
IT-
.
For TLV841M (MR pin > V
OH
) and TLV841C, when the voltage on VDD or when TLV841S SENSE pin monitoring
voltage rises above (V
IT+
+ V
HYS
), the output reset pin will de-assert and remain de-asserted until a reset
condition occurs again. Please refer to
datasheet for more information on the RESET output and how it
reacts to start up conditions and minimum values of VDD.
Propaga
on Detect Delay (t
P_HL
) = 26.4
s
VDD
RESET
Figure 4-2. TLV841EVM RESET Propagation Detect Delay
4.6 Reset Time Delay Programming (Program t
D
via C
T
) (TLV841C)
The TLV841C device variant has two options for setting the RESET time delay: connect CT pin to a capacitor to
GND, or leave CT pin floating. The reset time delay can be set to a minimum value of 80 µs by leaving the CT
pin floating, or a maximum value of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset
time delay (t
D
) can be programmed to any value within the range by connecting a capacitor no larger than 10 µF
between CT pin and GND. The relationship between external capacitor (C
CT_EXT
) at CT pin and the RESET time
t
D
= -ln (0.29) x R
CT
x C
CT_EXT
+ t
D
(no cap)
(1)
by plugging R
CT
and T
D(no cap)
given in the
Electrical Characteristics Table
in
datasheet.
t
D
= 618937 x C
CT_EXT
+ 80 µs
(2)
solves for external capacitor value (C
CT_EXT
)
C
CT_EXT
= (t
D
- 80 µs) ÷ 618937
(3)
EVM Setup and Operation
SNVU755A – JANUARY 2021 – REVISED JUNE 2021
TLV841EVM Voltage Supervisor User Guide
13
Copyright © 2021 Texas Instruments Incorporated
