U16 - 11
U16 - 15
U15 - 15
U15 - 11
R34
2.2K
C74
0.1uF
C73
0.1uF
SM7745HSV-22.5792M
4
3
2
1
Y2
22.5792M
Vcc
OUT
OE
GND
SM7745HSV-24.576M
3
2
1
Y3
24.576M
Vcc
OUT
4
OE
GND
C69
0.01uF
GND
C71
0.01uF
GND
GND
GND
GND
R33
10K
R35
10K
SN74LVC1G125DBVR
U13
5
4
3
2
1
SN74LVC1G125DBVR
1
2
3
4
5
U14
TP40
TP41
GND
GND
IOVD
IOVD
GND
GND
C70
0.1uF
GND
GND
ICS542
1
2
3
4
5
6
7
8
U12
C72
0.01uF
GND
R37
10K
GND
R38
10K
R36
10K
W41
2
1
W42
2
1
W43
2
1
W44
2
1
1
2
3
4
5
6
W45
MCLK
22.5792MHz/4
ADJCLK
1
2
3
4
5
6
W46
MCLK
22.5792MHz/4
ADJCLK
SN74LVC74APWR
U11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
SN74LVC1G07DBVR
1
2
3
4
5
U1
NC
GND
Y
VCC
A
SN74LVC1G07DBVR
1
2
3
4
5
U18
NC
GND
Y
VCC
A
SN74LVC1G07DBVR
1
2
3
4
5
U19
NC
GND
Y
VCC
A
SN74LVC1G07DBVR
1
2
3
4
5
U20
NC
GND
Y
VCC
A
IOVD
GND
R70
4.75K
R69
357
LOCK_SRC2
Green
+3.3VD
R72
4.75K
R71
357
READY_SRC1
Green
+3.3VD
R76
4.75K
R75
357
READY_SRC2
Green
+3.3VD
R74
4.75K
R73
357
LOCK_SRC1
Green
+3.3VD
GND
GND
GND
IOVD
IOVD
IOVD
SRC2_MCLK
SRC1_MCLK
MCLK
C112
0.1uF
C111
0.1uF
Input/12
Input/16
Input/4
Input/2
Input/8
Input/6
Installed
Removed
Removed
Removed
Removed
Installed
Power Down ALL
Installed
Installed
W43
W44
CLK
CLK/2
Install Jumper in W41 to
disable Y2 Output Clock
Install Jumper in W42 to
disable Y3 Output Clock
TO SRCs
SRC2_MCLK
SRC1_MCLK
(USB)
TLV320AIC3212EVM-U Schematic
Figure 20. Schematic, Sheet 6 of 8
20
TLV320AIC3212EVM-U Evaluation Module
SLAU435 – March 2012
Copyright © 2012, Texas Instruments Incorporated