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Program Description
3-13
Operation
3.5.2
Configuration Screen
This screen provides access to all of the configurable settings for the AIC26’s
A/D converter and reference, as shown in Figure 3−4.
Located on the right hand side of the screen are the programmable phase lock
loop (PLL) settings, which are not the A/D settings but the audio settings.
Figure 3−4. Configuration Screen
3.5.2.1
ADC Control Section
This section controls all of the parameters of the A/D converter. Each slider
controls one parameter, whose value is shown next to the slider. Each slider
is described below.
J
Resolution
Selects between 8-, 10-, and 12-bit resolution.
J
Conversion Clock
The internal clock which runs the A/D converter can run at 8, 4, 2, or 1 MHz.
When running at 8 MHz, only 8-bit resolution is possible; when running at
4 MHz, 8- or 10-bit resolution is possible, but 12-bit is not. These restric-
tions are reflected in the operation of this program, since only 1- or 2-MHz
clock rates allow 12-bit resolution to be chosen.
Summary of Contents for TLV320AIC26EVM
Page 12: ...1 4 THIS PAGE INTENTIONALLY LEFT BLANK ...
Page 15: ...Quick Start 2 3 Getting Started Figure 2 1 Default Software Screen ...
Page 16: ...2 4 THIS PAGE INTENTIONALLY LEFT BLANK ...
Page 26: ...Program Description 3 10 Figure 3 1 Data Acquisition Screen With ADC Registers Reading ...
Page 28: ...Program Description 3 12 Figure 3 3 Data Acquisition Screen With Boost Filter Parameters ...
Page 37: ...3 21 Operation THIS PAGE INTENTIONALLY LEFT BLANK ...
Page 39: ...Component Locations 4 2 4 1 Component Locations ...