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Switches
3-4
3.2.2
I
2
S Selection
The I
2
S bus on the AIC26 can interface with the onboard host processor, the
TAS1020B USB controller, or with other offboard external I
2
S processor or
devices. When SW1-1 is set ON, the manufacture default, the AIC26 I
2
S is
connected to the TAS1020B’s I
2
S. Otherwise, if SW1-1 is shifted to OFF, the
buffer between the on board I
2
S port is disabled so that an external I
2
S can
communicate with the AIC26 I
2
S port.
3.2.3
MCLK Selection
The AIC26 requires a proper MCLK for basic audio ADC/DAC functions. The
TAS1020B onboard processor generates an 11.2896-MHz frequency to
provide the MCLK. If an external MCLK is preferred, SW1-2 should be turned
off.
3.2.4
USB Reset
A reset signal output from the onboard TAS1020B processor can be used to
reset the the AIC26 whenever the TAS1020B is resetting. SW1−4 is used to
enable/disable the connection. By default, the connection is enabled. If the
processing is not active, the connection to the AIC26 should be disabled by
turning off SW1−4.
Summary of Contents for TLV320AIC26EVM
Page 12: ...1 4 THIS PAGE INTENTIONALLY LEFT BLANK ...
Page 15: ...Quick Start 2 3 Getting Started Figure 2 1 Default Software Screen ...
Page 16: ...2 4 THIS PAGE INTENTIONALLY LEFT BLANK ...
Page 26: ...Program Description 3 10 Figure 3 1 Data Acquisition Screen With ADC Registers Reading ...
Page 28: ...Program Description 3 12 Figure 3 3 Data Acquisition Screen With Boost Filter Parameters ...
Page 37: ...3 21 Operation THIS PAGE INTENTIONALLY LEFT BLANK ...
Page 39: ...Component Locations 4 2 4 1 Component Locations ...