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Texas Instruments ThunderSWITCH TNETX3270 s, Manual

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Texas Instruments ThunderSWITCH TNETX3270 s Manual Download Page 62

TNETX3270
ThunderSWITCH

 24/3 ETHERNET

 SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

 

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

62

POST OFFICE BOX 655303 

•

 DALLAS, TEXAS 75265

LED interface

operating characteristics over recommended operating conditions (see Figure 22)

NO.

PARAMETER

MIN

MAX

UNIT

1

tc(LEDCLK)

Cycle time, LEDCLK

96

ns

2

tw(LEDCLKH)

Pulse duration, LEDCLK high

38

58

ns

3

Number of LEDCLK pulses in burst

48†

4

tc(BURST)

Cycle time, LEDCLK burst

62

ms

5

td(LEDCLK)

Delay time, from LEDDATA to LEDCLK

↑

12

µ

s

6

td(LEDDATA)

Delay time, from LEDCLK

↑

to LEDDATA (1st LED invalid)

84

µ

s

† During hard reset, LEDCLK runs continuously.

LEDCLK

(output)

LEDDATA

(input/output)

5

2

6

1

3

4

First LED

Second LED

Last LED

First LED

Figure 22. LED

Summary of Contents for ThunderSWITCH TNETX3270 s

Page 1: ...teroperable Support for IEEE Std 802 1Q VLAN Supports IEEE Std 802 1D Spanning Tree Thirty Two Assignable Virtual LANs VLANs Multiple Forwarding Modes 2K Total Addresses Supported Port Mirroring D IEEE Std 1149 1 JTAG Interface 3 3 V Signals D 2 5 V Process With 3 3 V Drive I O D Packaged in 240 Terminal Plastic Quad Flatpack Eight Ports 16 23 10 Mbit s Controller MAC Controller MAC Controller MAC...

Page 2: ...to provide up to 600 Mbit s switch to switch connections The TNETX3270 incorporates an internal content addressable memory CAM capable of supporting 2 048 end stations from a single switch In addition the device supports 32 user configurable VLAN broadcast domains IEEE Std 802 1Q which allows IEEE Std 802 1P priority support interoperability IEEE Std 802 3X full duplex flow control and a collision...

Page 3: ... Up OSCIN and RESET 63 Mechanical Data 64 Description 2 PGV Package Terminal Layout 4 TNETX3270 Interface Block Diagram 5 Terminal Functions 6 DIO Register Groups 13 Interface Description 18 DIO Interface 18 Receiving Transmitting Management Frames 18 State of DIO Signals During Hardware Reset 18 Network Management Port 19 MII Serial Management Interface PHY Management 22 10 Mbit s and 10 100 Mbit...

Page 4: ...M26CRS VDD 2 5V M26COL M26TXER GND M26TXEN M26TXD3 M26TXD2 M26TXD1 M26TXD0 M26TCLK GND M25FORCE10 M25FORCEHD M25LINK VDD 2 5V M25RXER M25RXDV GND M25RXD3 VDD 3 3V M25RXD2 M25RXD1 M25RXD0 GND M25RCLK M25CRS M25COL VDD 2 5V M25TXER M25TXEN M25TXD3 1 5 10 15 20 25 35 40 45 50 55 60 180 175 170 165 160 155 150 145 140 135 130 125 121 DD25 DD24 V DD23 DD22 GND DD21 DD19 DD18 DD17 DD16 DD15 DD14 DD12 DD...

Page 5: ...eing monitored Data Path LED Interface TH0RENEG TH1CLK TH1TXD3 TH1TXD0 TH1TXEN TH1COL TH1CRS TH1SYNC TH1RXD3 TH1RXD0 TH1RXDV TH1LINK TH1RENEG TH2CLK TH2TXD3 TH2TXD0 TH2TXEN TH2COL TH2CRS TH2SYNC TH2RXD3 TH2RXD0 TH2RXDV TH2LINK TH2RENEG CPU Interface SDRAM Controller Controller MAC Controller MAC Controller MAC Controller MAC Controller MAC Controller MAC Controller MAC Controller MAC Controller MA...

Page 6: ...renegotiate A 1 0 1 sequence output on THxRENEG causes flow control and half full duplex for a port to be renegotiated with its companion physical layer PHY device These THxRENEG terminals connect to IFFORCEHD on TNETE2008 TH0RXD3 TH0RXD2 TH0RXD1 TH0RXD0 TH1RXD3 TH1RXD2 TH1RXD1 TH1RXD0 TH2RXD3 TH2RXD2 TH2RXD1 TH2RXD0 231 230 228 227 11 10 9 7 30 29 28 27 I Pullup Interface receive data The receive...

Page 7: ... collision on that port In full duplex operation transmission of new frames does not start if this terminal is asserted M24CRS M25CRS M26CRS 43 66 92 I Pulldown Carrier sense MxxCRS indicates a frame carrier signal is being received M24FORCE10 M25FORCE10 M26FORCE10 54 80 104 I O Pullup Speed selection force 10 Mbit s is active low If pulled low by either the TNETX3270 or a PHY the port operates at...

Page 8: ...Pulldown Receive error MxxRXER indicates a coding error on received data M24TCLK M25TCLK M26TCLK 33 56 82 I Pullup Transmit clock Transmit clock source from the attached PHY or PMI device M24TXD3 M24TXD2 M24TXD1 M24TXD0 M25TXD3 M25TXD2 M25TXD1 M25TXD0 M26TXD3 M26TXD2 M26TXD1 M26TXD0 38 37 36 35 61 60 59 57 86 85 84 83 O None Transmit data nibble transmit data When MxxTXEN is asserted these signals...

Page 9: ...nd DW determines the SDRAM commands DCLK 193 O None SDRAM clock 83 33 MHz clock to the SDRAMs SDRAM commands addresses and data are sampled by the SDRAM on the rising edge of this clock DD31 DD30 DD29 DD28 DD27 DD26 DD25 DD24 DD23 DD22 DD21 DD20 DD19 DD18 DD17 DD16 DD15 DD14 DD13 DD12 DD11 DD10 DD09 DD08 DD07 DD06 DD05 DD04 DD03 DD02 DD01 DD00 187 186 185 183 182 181 180 179 177 176 174 173 172 17...

Page 10: ...er each address SDATA7 SDATA6 SDATA5 SDATA4 SDATA3 SDATA2 SDATA1 SDATA0 136 135 133 131 130 129 127 126 I O Pullup DIO data interface bus byte wide bidirectional DIO port SDATA7 is the most significant bit and SDATA0 is the least significant bit SINT 140 O None DIO interrupt line interrupt to the attached microprocessor The interrupt originating event is stored in the Int register SRDY 139 O Pullu...

Page 11: ...CPU is present LED interface TERMINAL I O INTERNAL DESCRIPTION NAME NO I O RESISTOR DESCRIPTION LEDCLK 113 O None LED clock serial shift clock for the LED status data LEDDATA 114 O None LED data serial LED status data LEDDATA is active low All LED information port link activity status software status flow status and fault status is sent via this serial interface JTAG interface TERMINAL I O INTERNA...

Page 12: ... 94 100 128 134 141 148 154 160 175 188 194 201 208 214 220 235 None Ground GND is the 0 V reference for the device All GND terminals must be connected VDD 3 3V 12 72 109 122 132 163 169 192 229 None 3 3 V supply voltage Power for the input output and I O terminals VDD 2 5V 4 17 31 45 58 64 77 91 105 118 124 137 151 165 178 184 197 211 225 238 None 2 5 V supply voltage Power for the core summary o...

Page 13: ...ster groups Table 1 Internal Register and Statistics Memory Map REGISTERS LOADABLE USING 24C02 EEPROM LOADABLE USING 24C08 EEPROM DIO ADDRESS RANGE Port configuration Yes Yes 0x0000 0x002F Spanning tree Yes Yes 0x0030 0x007F Trunking Yes Yes 0x0080 0x0088 VLAN No Yes 0x0089 0x03FF Port status No No 0x0400 0x043F Address configuration No No 0x0440 0x08FF Port statistics No No 0x0900 0xFFFF ...

Page 14: ...0x0028 Port23control Port22control 0x002C Port25control Port24control 0x0030 Reserved Port26control 0x0034 Reserved Reserved 0x0038 0x003F Reserved UnkVLANport Mirrorport Uplinkport 0x0040 Reserved Aging threshold 0x0044 Reserved 0x0048 0x004F Nlearnports 0x0050 Txblockports 0x0054 Rxuniblockports 0x0058 Rxmultiblockports 0x005C Unkuniports 0x0060 Unkmultiports 0x0064 Unksrcports 0x0068 UnkVLANint...

Page 15: ...AN9ports 0x0124 VLAN10ports 0x0128 VLAN11ports 0x012C VLAN12ports 0x0130 VLAN13ports 0x0134 VLAN14ports 0x0138 VLAN15ports 0x013C VLAN16ports 0x0140 VLAN17ports 0x0144 VLAN18ports 0x0148 VLAN19ports 0x014C VLAN20ports 0x0150 VLAN21ports 0x0154 VLAN22ports 0x0158 VLAN23ports 0x015C VLAN24ports 0x0160 VLAN25ports 0x0164 VLAN26ports 0x0168 VLAN27ports 0x016C VLAN28ports 0x0170 VLAN29ports 0x0174 VLAN...

Page 16: ... Port6Qtag 0x038C Port9Qtag Port8Qtag 0x0390 Port11Qtag Port10Qtag 0x0394 Port13Qtag Port12Qtag 0x0398 Port15Qtag Port14Qtag 0x039C Port17Qtag Port16Qtag 0x03A0 Port19Qtag Port18Qtag 0x03A4 Port21Qtag Port20Qtag 0x03A8 Port23Qtag Port22Qtag 0x03AC Port25Qtag Port24Qtag 0x03B0 Reserved Port26Qtag 0x03B4 Reserved 0x03B8 0x03FF Port1status Port0status 0x0400 Port3status Port2status 0x0404 Port5status...

Page 17: ...24 Agednode 39 32 Agednode 47 40 0x0464 AgedVLAN Agedport Agednode 7 0 Agednode 15 8 0x0468 Delnode 23 16 Delnode 31 24 Delnode 39 32 Delnode 47 40 0x046C DelVLAN Delport Delnode 7 0 Delnode 15 8 0x0470 Agingcounter Numnodes 0x0474 Reserved 0x0478 0x07FF Reserved DMAaddress 0x0800 Reserved Int 0x0804 Reserved Intenable 0x0808 Systest Freestacklength 0x080C RAMaddress 0x0810 Reserved RAMdata 0x0814...

Page 18: ...d by the switch and routed to the destination port s Frames that were routed to this port from any of the switch ports are placed in a queue until the host is ready to read them via the NMTxcontrol and NMdata registers They then are effectively transmitted out of the switch SDMA can be used to transmit or receive management frames the SAD1 SAD0 pins are ignored when SDMA is asserted see Table 3 Wh...

Page 19: ...aders depending on how the frame was originally received full duplex NM port The NM port can intermix reception and transmission as desired The direction of the NMdata access i e read or write determines whether a byte is removed from the transmit queue or added to the receive queue The DIO interface is half duplex since it can do only a read or write at one time NM bandwidth and priority The NM p...

Page 20: ...t the IEEE Std 802 1Q TPID of 81 00 ethertype constant value into the TPID field if the frame needs to be restored to a normal IEEE Std 802 1Q frame format which passes a CRC check To provide a CRC word which includes the header the NM port generates a new CRC word as the frame is being read out It simultaneously checks the existing CRC in the frame and if an error is found ensures that the final ...

Page 21: ...M port transmissions this pretends that IEEE Std 802 1Q TPID of 81 00 ethertype constant is present in the TPID field If a CRC error or parity error is detected the frame is discarded When crctype indicates that the header is included the NM port regenerates CRC to exclude the header during the reception process this converts the frame into the required internal frame format D crc 1 in NMRxcontrol...

Page 22: ... through the SIO register The direction of MDIO is controlled by the SIO register In addition a third signal MRESET is provided to allow hardware reset of PHYs that support it All three signals have internal pullup resistors since they all can be placed into high impedance via the MDIOEN bit of the SIO register to allow another bus master The interface does not implement timing or data structure T...

Page 23: ...e performance optimization APO transmit pacing Each Ethernet MAC incorporates APO logic This can be enabled on an individual port basis When enabled the MAC uses transmission pacing to enhance performance when connected on networks using other transmit pacing capable MACs Adaptive performance pacing introduces delays into the normal transmission of frames delaying transmission attempts between sta...

Page 24: ... on different ports require transmission on the same port s and when frames are repeatedly received on ports that are at a higher speed than the ports on which they are transmitted This is likely to be exacerbated by the reception of multicast frames which typically require transmission on several ports When the backlog grows to such an extent that the free buffer stack is nearly empty flow contro...

Page 25: ... PORT 0 0000 Port 00 0 0001 Port 01 0 0010 Port 02 0 0011 Port 03 0 0100 Port 04 0 0101 Port 05 0 0110 Port 06 0 0111 Port 07 0 1000 Port 08 0 1001 Port 09 0 1010 Port 10 0 1011 Port 11 0 1100 Port 12 0 1101 Port 13 0 1110 Port 14 0 1111 Port 15 1 0000 Port 16 1 0001 Port 17 1 0010 Port 18 1 0011 Port 19 1 0100 Port 20 1 0101 Port 21 1 0110 Port 22 1 0111 Port 23 1 1000 Port 24 1 1001 Port 25 1 10...

Page 26: ...n bit is set If this is the case the frame is received and handled like a unicast frame such frames can be cut through If more than one bit is set the frame is handled as an in order broadcast and cannot be cut through The frame is routed to all the port s specified regardless of whether the destination address is unicast or multicast i e the destination address is not examined If all 28 tag bits ...

Page 27: ... If a DIO write is attempted SRDY is held high until the download has completed The EEPROM size is detected automatically according to the address assigned to the EEPROM D 2048 bits organized as a 256 8 EEPROM should have its A0 A1 and A2 pins tied low D 8192 bits organized as a 1024 8 EEPROM should have its A0 and A1 pins tied low and A2 pin tied high TNETX3270 EDIO ECLK 24C0x Flash EEPROM SCL SD...

Page 28: ... with the SIO register The EDIO pin is shared with the SIO register edata bit The edata and etxen bits must not both be set to 1 when the load bit is set or the EDIO pin is held at resistive 1 and the EEPROM load fails The value of the eclk bit in SIO is don t care when load is set but to ensure the EEPROM does not see a glitch on its clock signal the load bit should not be set until the minimum c...

Page 29: ...nal pins to become high impedance All pullup and pulldown resistors are disabled LED interface This interface allows a visual status for each port to be displayed In addition the state of the internal flow control and fault functions are displayed along with 12 software controllable LEDs Each port has a single LED which can convey three states see Table 9 Table 9 LED States STATE DISPLAY No link O...

Page 30: ...ring the previous 1 16th of a second 48 48 FAULT Fault LED indicates the EEPROM CRC is invalid an external DRAM parity error has occurred the fitled in LEDControl has been set The CRC and parity error indications are cleared by hardware reset terminal or DIO The CRC error indication also is cleared by setting load to 1 The parity error indication also is cleared by setting start to 1 lamp test Whe...

Page 31: ...runs synchronous to the PHY generated 20 MHz clock IFCLK The MAC to PHY information for the first port in each group of eight i e port 00 port 08 or port 16 is presented on the interface when the THxSYNC terminal is high The next clock cycle that the interface carries is the information for the second port This process continues for all eight ports each using the interface for one cycle When all p...

Page 32: ...EN M00TXEN M01TXEN M01FHD M02FHD M03FHD M04FHD M05FHD M06FHD M07FHD M00FHD M01FHD M03COL M04COL M05COL M06COL M07COL M00COL M01COL M02COL M03COL M02CRS M02LINK M02RXD M02RXDV PORT SYNC TXD3 TXD0 TXEN FORCEHD COL CRS LINK RXD3 RXD0 RXDV M03CRS M03LINK M03RXD M03RXDV M04CRS M04LINK M04RXD M04RXDV M05CRS M05LINK M05RXD M05RXDV M06CRS M06LINK M06RXD M06RXDV M07CRS M07LINK M07RXD M07RXDV M00CRS M00LINK...

Page 33: ...n 750 ms Min Clock Runs Continuously THxTXEN output THxCLK input THxTXD3 output THxTXD2 output THxTXD1 output THxTXD0 output THxLINK input THxRXDV input THxRXD3 input THxRENEG output THxRXD2 input THxRXD1 input THxRXD0 input Will be 0 Will be 0 Will be 0 1 pause granted 1 half duplex 1 pause granted THxCLK input THxLINK input THxRXDX input THxRXD Final Value THxLINK 1 THxRXD final value latched Mu...

Page 34: ...XD0 MRXD0 MxxRXDV MRXDV MxxRXER MRXER MxxLINK SLINK MDCLK MDCLK MDIO MDIO MRESET MRST Where xx 24 25 or 26 y 0 3 Other differences from the 10 Mbit s ports are noted in following paragraphs 10 100 Mbit s port configuration The 100 Mbit s ports 24 26 can negotiate with the PHY speed and duplex at power up via the EEPROM contents using the MxxFORCE10 and MxxFORCEHD terminals respectively Each of the...

Page 35: ... 100 1 Driven 0 by TNETX3270 0 10 X Driven 0 by PHY 0 10 Table 14 Duplex Configuration MxxFORCEHD Portxcontrol reqhd MxxFORCEHD Portxstatus DUPLEX OUTCOME 0 Floating 1 1 Full duplex 1 Driven 0 by TNETX3270 0 Half duplex X Driven 0 by PHY 0 Half duplex 10 100 Mbit s port configuration in a nonmanaged switch The 10 100 Mbit s ports can be configured in a nonmanaged switch using the following procedu...

Page 36: ...he operating state of the PHYs subsequently can be altered by using the IEEE Std 802 3u MII management interface Any change of state should be reflected on the values presented on MxxFORCE10 and MxxFORCEHD so that the MACs are similarly reconfigured Or 1 MxxFORCE10 and MxxFORCEHD should not be connected to anything 2 Software uses the IEEE Std 802 3u MII management interface to configure the PHYs ...

Page 37: ...ess DA03 A3 Row address column address DA02 A2 Row address column address DA01 A1 Row address column address DA00 A0 Row address column address DRAS RAS Row address strobe DCAS CAS Column address strobe DW W Write enable DCLK CLK Clock DD31 DD16 DQ15 DQ0 SDRAM1 Data I O 16 SDRAMs DD15 DD00 DQ15 DQ0 SDRAM0 DD31 DD24 DQ7 DQ0 SDRAM3 Data I O 8 SDRAMs DD23 DD16 DQ7 DQ0 SDRAM2 DD15 DD08 DQ7 DQ0 SDRAM1 ...

Page 38: ... an active CLK The system designer must ensure that this inactivity period is observed while TNETX3270 is held in hardware or software reset Table 17 shows the state of the SDRAM interface terminals during hardware or software reset Table 17 SDRAM Interface Terminal State During Hardware or Software Reset TNETX3270 TERMINAL STATE DURING RESET DA13 DA00 Driven high DRAS Driven high DCAS Driven high...

Page 39: ...001 Header Stripped Header Retained VLANnQID VLAN ID Lookup Source Address SA Destination Address DA Reset 1st Location 0x001 All Others 0x000 No Match VLAN and Ethernet Addresses VLAN ADDR Reset to All 0s SA DA VLAN VLAN Index Frame Routing Algorithm UnkUniPorts UnkMultiPorts UnkSrcPorts UnkVLANPort TxBlockPorts RxUniBlockPorts RxMultiBlockPorts MirrorPort UplinkPort TrunkMapx TrunkxPorts NLearnP...

Page 40: ...g process Only one of the VLAN IDs match if they have been programmed correctly If more than one matches the hardware chooses one of them new VLAN member The IALE checks to see if the source port already has been declared as a member of this VLAN If not then an interrupt is provided to allow the attached CPU to add this port as a new member of the VLAN IEEE Std 802 1Q headers transmission The IEEE...

Page 41: ...he age for this address has not expired table full aging In table full aging the oldest address or one of the oldest addresses if there is more than one is automatically deleted from the IALE records only if the table is full and a new address needs to be added to the table In this mode the age stamp for the addresses is not refreshed frame routing determination When a frame is received its 48 bit...

Page 42: ... Yes Source Port Blocked by RxMultiBlockPorts and Dest Nblck 0 Source Port Blocked by RxMultiBlockPorts Yes Source Port Blocked by RxUniBlockPorts Destination is Multicast Yes Yes Source Port Blocked by RxMultiBlockPorts or UnkVLAN 0 No No No No No No Port Routing Code Port Code From Records Port Routing Code Port Vector From Records Port Routing Code UnkMultiPorts Port Routing Code UnkUniPorts Po...

Page 43: ...ove Source Port and other trunk members From Port Routing Code Source Address Found Source Port 1 in NLearnPorts No AND UnkSrcPorts With VLAN VLANnports Then OR With Port Routing Code Yes No Source Locked Bit 1 Yes Source Port Moved Source Secure Bit 1 No secvio Yes Yes Discard Frame chng No To C Continued No Yes Stayed Within a Trunk Yes Source Port 1 in RingPorts No Yes Unknown Source Figure 9 F...

Page 44: ... Source Port UplinkPort Then Include UplinkPort in Port Routing Code No Lshare 1 No Port Routing Code is Adjusted by Trunking Algorithm see Note A Destination Found Yes No Port Routing Code is Adjusted by Load Sharing Algorithm see Note A Yes NOTE A See Port Trunking Load Sharing Port Routing Code 0 Send Frame to Ports Indicated by Port Routing Code No Yes Discard Frame D C Figure 9 Frame Routing ...

Page 45: ... most significant bit of the map index Bits 31 16 are XORed to produce the middle of the map index Bits 15 0 are XORed to produce the least significant bit of the map index Once assigned the tx port for a unicast packet is static flow control The switch incorporates two forms of flow control collision based and IEEE Std 802 3 pause frames In either case the switch recognizes when it is becoming co...

Page 46: ...multicast destination address 01 80 C2 00 00 01 D 48 bit source address is read from the Devnode register when transmitted by this device D 16 bit length type field containing the value 88 08 D 16 bit pause opcode equal to 00 01 D 16 bit pausetime This specifies a nonzero number of pausequanta A pausequantum is 512 bit times D Padding as required desired D 32 bit frame check sequence CRC word All ...

Page 47: ... to the pause_time value of the new pause frame any remaining pause time from the previous pause frame is disregarded If the pause bit in Portxstatus ever becomes a 0 because pause frames are no longer supported the pause timer immediately expires A port does not begin to transmit any new data frame any later than 512 bit times after a pause frame with a nonzero pause time has been received RXDV g...

Page 48: ...registers and program these tags into the VLANnQID registers D The VLANnports register associated with each of the VLANnQID registers should have only one bit set indicating the port to which frames containing that IEEE Std 802 3 tag should be routed D Rxacc and Txacc for each port must be 1 This causes the port to add the VID from its PortxQtag to the frame on reception and strip the tag before t...

Page 49: ...wn in Figure 10 By using multicast broadcast frames traffic can be routed selectively between ports involved in the test or return the frame directly before retransmission on the uplink Software control of the external PHYs is required to configure them for loopback If the internal PCS is in use port configured in PMA mode loopback in PCSxcontrol also must be asserted This causes MxxEWRAP to be hi...

Page 50: ...led if it is 0 If Mirrorport selects a port that is a member of a trunk only that single specific port is mirrored Frame traffic on the other trunk port s is not mirrored The Uplinkport register should not select a port within a trunk undesired behavior can occur if this is done copy to uplink If destination address is a unicast and the cuplnk bit of its address record is set to 1 via a DIO add wh...

Page 51: ...ed under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 Applies to external input buffers Level shifting inputs are relative to VDD 3 3V 2 Applies to external output buffers Level shifting outputs are relative to VDD 3 3V recommended operating conditions MIN NOM MAX UNIT VDD 2 5V Supply voltag...

Page 52: ...ch the signal is said to be no longer low is 0 8 V and the level at which the signal is said to be high is 2 V as shown in the following The rise and fall times are not specified but are assumed to be those of standard TTL devices which are typically 1 5 ns 0 8 V low 2 V high 1 4 V test measurement The test and load circuit shown in Figure 12 represents the programmable load of the tester pin that...

Page 53: ... ensure complete initialization of the internal circuitry of the TNETX3270 before there is any valid activity across the interface 5 For receive data the TNETE2008 asserts the THxCOL signal during the appropriate slot time if it was asserted for any of the four bits of data corresponding to that slot time 6 For receive data the TNETE2008 asserts the THxRXDV signal only if there are four valid bits...

Page 54: ... MxxRCLKH Pulse duration MxxRCLK high 14 ns 4 tsu MxxRXD Setup time MxxRXD3 MxxRXD0 valid before MxxRCLK 5 ns 4 tsu MxxRXDV Setup time MxxRXDV valid before MxxRCLK 5 ns 4 tsu MxxRXER Setup time MxxRXER valid before MxxRCLK 5 ns 5 th MxxRXD Hold time MxxRXD3 MxxRXD0 valid after MxxRCLK 5 ns 5 th MxxRXDV Hold time MxxRXDV valid after MxxRCLK 5 ns 5 th MxxRXER Hold time MxxRXER valid after MxxRCLK 5 ...

Page 55: ... 15 NO PARAMETER MIN MAX UNIT 4 td MxxTXD Delay time from MxxTCLK to MxxTXD3 MxxTXD0 valid 0 25 ns 4 td MxxTXEN Delay time from MxxTCLK to MxxTXEN valid 0 25 ns 4 td MxxTXER Delay time from MxxTCLK to MxxTXER valid 0 25 ns xx ports 24 25 and 26 NOTE 8 Both MxxCRS and MxxCOL are driven asynchronously by the PHY MxxTXD3 MxxTXD0 is driven by the reconciliation sublayer synchronous to the MxxTCLK MxxT...

Page 56: ...o REFR to next ACTV or REFR 120 ns tRAS Row active time ACTV to DCAB 72 ns tRP Row recharge time DCAB to ACTV REFR or MRS 36 ns tRCD Row to column delay ACTV to READ or WRT 36 ns tAC3 Column access time READ CAS latency READ to data sample 36 ns nCCD Column address to column address WRT to next READ or WRT or READ to next READ 24 ns nCWL Last data or write to new column address WRT to next READ or...

Page 57: ...nable time from DCLK to before DD31 DD00 driven read cycle 0 ns 8 tdis DDW Disable time from DCLK to after DD31 DD00 after final write cycle to Z state 10 ns 9 tdis DDR Disable time from DCLK to after DD31 DD00 after final read cycle to Z state 11 ns 10 td DDW 1 Delay time from DD valid to DCLK write cycle 4 ns 11 td DDW 2 Delay time from DCLK to DD31 DD00 Z state write cycle 2 ns 12 td DDR 1 Dela...

Page 58: ...ristics over recommended operating conditions see Figure 18 NO PARAMETER MIN MAX UNIT 6 tw SRDYH Pulse duration SRDY high 12 ns 7 td SRNW Delay time from SRDY to SRNW 0 ns 8 td SAD Delay time from SRDY to SAD1 SAD0 and SDMA invalid 0 ns 9 td SDATA Delay time from SRDY to SDATA7 SDATA0 invalid 0 ns 10 td SCS Delay time from SRDY to SCS 0 ns 11 td SRDY 1 Delay time from SCS to SRDY 0 ns 12 td SRDY 2...

Page 59: ...lay time from SRDY to SRNW 0 ns 7 td SAD Delay time from SRDY to SAD1 SAD0 and SDMA invalid 0 ns 8 td SCS Delay time from SRDY to SCS 0 ns 9 td SRDY Delay time from SDATA7 SDATA0 to SRDY 0 ns 10 td SRDYZH Delay time from SCS to SRDY 0 ns 11 td SRDY 2 Delay time from SCS to SRDY 0 ns 12 td SDATAZ Delay time from SCS to SDATA7 SDATA0 Z state 0 6 ns 13 td SRDY 3 Delay time from SCS to SRDY 0 12 ns Wh...

Page 60: ... from OSCIN to MDIO valid write 11 ns 4 td MDCLK Delay time from OSCIN to MDCLK 11 ns 5 td MRESET Delay time from OSCIN to MRESET 11 ns 6 tdis MDIO Disable time from OSCIN to after MDIO to Z state read 11 ns 7 tdis MDCLK Disable time from OSCIN to after MDCLK to Z state 11 ns 8 tdis MRESET Disable time from OSCIN to after MRESET to Z state 11 ns 9 ten MDIO Enable time from OSCIN to before MDIO val...

Page 61: ... 5 5 µs 3 td ECLKL EDIOX Delay time from ECLK to EDIO changing see Note 10 0 0 µs 4 td EDIOV ECLKH Delay time from EDIO valid output to ECLK 0 0 µs 5 td ECLKL EDIOV Delay time from ECLK to EDIO valid 0 0 µs 6 td ECLKL EDIOX Delay time from ECLK to EDIO changing see Note 11 0 0 µs 7 td ECLKH EDIOX Delay time from ECLK to EDIO invalid 5 5 µs 8 td EDIOV ECLKH Delay time from EDIO valid input to ECLK ...

Page 62: ... Figure 22 NO PARAMETER MIN MAX UNIT 1 tc LEDCLK Cycle time LEDCLK 96 ns 2 tw LEDCLKH Pulse duration LEDCLK high 38 58 ns 3 Number of LEDCLK pulses in burst 48 4 tc BURST Cycle time LEDCLK burst 62 ms 5 td LEDCLK Delay time from LEDDATA to LEDCLK 12 µs 6 td LEDDATA Delay time from LEDCLK to LEDDATA 1st LED invalid 84 µs During hard reset LEDCLK runs continuously LEDCLK output LEDDATA input output ...

Page 63: ... Pulse duration RESET low 200 µs 5 tsu RESET Setup time RESET low before OSCIN 7 ns 6 th RESET Hold time RESET low after OSCIN 3 ns 7 td OSCIN Delay time from OSCIN invalid to OSCIN valid stable 25 ms 8 td RESET Delay time from OSCIN stable to RESET 25 ms 9 tt OSCIN Transition time OSCIN rise and fall 2 ns RESET must be held low at least 25 ms after both power supplies are stable and OSCIN has rea...

Page 64: ...PQFP G240 PLASTIC QUAD FLATPACK DIE DOWN 4040247 A 03 95 121 0 27 0 17 120 Seating Plane 60 61 Heat Slug 180 181 SQ SQ 32 20 31 80 34 80 34 40 29 50 TYP 1 240 4 20 MAX 3 80 TYP 0 08 0 50 M 0 08 0 16 NOM 0 25 0 75 0 50 0 25 MIN 0 7 Gage Plane NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Thermally enhanced molded plastic package with a heat sl...

Page 65: ...CONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to ...

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