![background image](http://html.mh-extra.com/html/texas-instruments/thunderswitch-tnetx3270-s/thunderswitch-tnetx3270-s_manual_1097140059.webp)
TNETX3270
ThunderSWITCH
24/3 ETHERNET
SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999
59
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
DIO/DMA read cycle
timing requirements (see Figure 19)
NO.
MIN
MAX
UNIT
1
tw(SCSL)
Pulse duration, SCS low
ns
2
tw(SCSH)
Pulse duration, SCS high
14
ns
3
tsu(SRNW)
Setup time, SRNW high before SCS
↓
0
ns
4
tsu(SAD)
Setup time, SAD1–SAD0 and SDMA valid before SCS
↓
0
ns
operating characteristics over recommended operating conditions (see Figure 19)
NO.
PARAMETER
MIN
MAX
UNIT
5
tw(SRDYH)
Pulse duration, SRDY high
12
ns
6
td(SRNW)
Delay time, from SRDY
↓
to SRNW
↓
0
ns
7
td(SAD)
Delay time, from SRDY
↓
to SAD1–SAD0 and SDMA invalid
0
ns
8
td(SCS)
Delay time, from SRDY
↓
to SCS
↑
0
ns
9
td(SRDY)
Delay time, from SDATA7–SDATA0 to SRDY
↓
0
ns
10
td(SRDYZH) Delay time, from SCS
↓
to SRDY
↑
0
ns
11
td(SRDY)2
Delay time, from SCS
↓
to SRDY
↓
†
0
ns
12
td(SDATAZ)
Delay time, from SCS
↑
to SDATA7–SDATA0 Z state
0
6
ns
13
td(SRDY)3
Delay time, from SCS
↑
to SRDY
↑
0
12
ns
† When the switch is performing certain internal operations (e.g., EEPROM load), there may be a considerable delay (approximately 25–100 ms)
between SCS being asserted and SRDY being asserted.
SAD1–SAD0,
SDMA
(inputs)
SRNW
(input)
SCS
(input)
ÎÎÎ
ÎÎÎ
ÎÎÎ
1
11
4
3
10
8
7
9
5
12
SDATA7–
SDATA0
(outputs)
SRDY
(output)
6
2
13
Z
Z
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Z
ÎÎÎÎÎ
ÎÎÎÎÎ
Figure 19. DIO/DMA Read Cycle