4-2
Figure 4–1. Common Mode Input VREF/2 – 1Vp-p Input Span (top/bottom mode)
A/D
_
+
SHA
PGA
ADC
REF
0.1
µ
F
10
µ
F
0.1
µ
F
0.1
µ
F
REFTF
REFBF
+
–
1 V
AIN
1 V
0 V
REFTS
REFBS
MODE
AVDD
VREF
REFSENSE
THS1030/31
Figure 4–2. Common Mode Input VREF/2 – 2Vp-p Input Span (top/bottom mode)
A/D
_
+
SHA
PGA
ADC
REF
0.1
µ
F
10
µ
F
0.1
µ
F
0.1
µ
F
REFTF
REFBF
+
–
1 V
AIN
2 V
0 V
REFTS
REFBS
MODE
AVDD
VREF
REFSENSE
THS1030/31
Summary of Contents for THS1030/31EVM
Page 4: ...iv...
Page 8: ...viii...
Page 12: ...1 4...
Page 15: ...PCB Layout 2 3 Physical Description Figure 2 2 Silk Bottom...
Page 16: ...PCB Layout 2 4 Figure 2 3 Top...
Page 17: ...PCB Layout 2 5 Physical Description Figure 2 4 Inner 1...
Page 18: ...PCB Layout 2 6 Figure 2 5 Inner 2...
Page 19: ...PCB Layout 2 7 Physical Description Figure 2 6 Bottom...
Page 22: ...2 10...
Page 38: ...4 8 Modes of Operation...
